1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Microsemi Corporation
6 #ifndef _MSCC_JR2_ICPU_CFG_H_
7 #define _MSCC_JR2_ICPU_CFG_H_
9 #include <linux/bitops.h>
11 #define ICPU_GPR(x) (0x4 * (x))
12 #define ICPU_GPR_RSZ 0x4
14 #define ICPU_RESET 0x20
16 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
17 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
18 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
19 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL 0x24
23 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(15)
24 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(14)
25 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(13)
26 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(12)
27 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(11)
28 #define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(10)
29 #define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(9)
30 #define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(8)
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 6) & GENMASK(7, 6))
32 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(7, 6)
33 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(7, 6)) >> 4)
34 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER(x) (((x) << 4) & GENMASK(5, 4))
35 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER_M GENMASK(5, 4)
36 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
37 #define ICPU_GENERAL_CTRL_SSI_MST_CONTENTION BIT(3)
38 #define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2)
39 #define ICPU_GENERAL_CTRL_CPU_DIS BIT(1)
40 #define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
42 #define ICPU_SPI_MST_CFG 0x3c
44 #define ICPU_SPI_MST_CFG_A32B_ENA BIT(11)
45 #define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
46 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
47 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
48 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
49 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
50 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
52 #define ICPU_SW_MODE 0x50
54 #define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
55 #define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
56 #define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
57 #define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
58 #define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
59 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
60 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
61 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
62 #define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
63 #define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
64 #define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
65 #define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
67 #define ICPU_INTR_ENA 0x88
69 #define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x))
70 #define ICPU_DST_INTR_MAP_RSZ 0x4
72 #define ICPU_TIMER_TICK_DIV 0x108
74 #define ICPU_TIMER_VALUE(x) (0x10c + 0x4 * (x))
75 #define ICPU_TIMER_VALUE_RSZ 0x4
77 #define ICPU_TIMER_CTRL(x) (0x124 + 0x4 * (x))
78 #define ICPU_TIMER_CTRL_RSZ 0x4
80 #define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3)
81 #define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2)
82 #define ICPU_TIMER_CTRL_TIMER_ENA BIT(1)
83 #define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0)
85 #define ICPU_MEMCTRL_CTRL 0x130
87 #define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
88 #define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
89 #define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
90 #define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
92 #define ICPU_MEMCTRL_CFG 0x134
94 #define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
95 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
96 #define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
97 #define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
98 #define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
99 #define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
100 #define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
101 #define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
102 #define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
103 #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
104 #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
105 #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
106 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
107 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
109 #define ICPU_MEMCTRL_STAT 0x138
111 #define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
112 #define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
113 #define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
114 #define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
115 #define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
116 #define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
118 #define ICPU_MEMCTRL_REF_PERIOD 0x13c
120 #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
121 #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
122 #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
123 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
124 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
126 #define ICPU_MEMCTRL_ZQCAL 0x140
128 #define ICPU_MEMCTRL_ZQCAL_ZQCAL_LONG BIT(1)
129 #define ICPU_MEMCTRL_ZQCAL_ZQCAL_SHORT BIT(0)
131 #define ICPU_MEMCTRL_TIMING0 0x144
133 #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
134 #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
135 #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
136 #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
137 #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
138 #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
139 #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
140 #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
141 #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
142 #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
143 #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
144 #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
145 #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
146 #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
147 #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
148 #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
149 #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
150 #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
151 #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
152 #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
153 #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
154 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
155 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
157 #define ICPU_MEMCTRL_TIMING1 0x148
159 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
160 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
161 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
162 #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
163 #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
164 #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
165 #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
166 #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
167 #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
168 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
169 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
170 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
171 #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
172 #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
173 #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
174 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
175 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
177 #define ICPU_MEMCTRL_TIMING2 0x14c
179 #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
180 #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
181 #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
182 #define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
183 #define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
184 #define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
185 #define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
186 #define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
187 #define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
188 #define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0))
189 #define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0)
191 #define ICPU_MEMCTRL_TIMING3 0x150
193 #define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
194 #define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
195 #define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
196 #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
197 #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
198 #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
199 #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
200 #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
201 #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
202 #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
203 #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
204 #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
205 #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
206 #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
208 #define ICPU_MEMCTRL_TIMING4 0x154
210 #define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY(x) (((x) << 20) & GENMASK(31, 20))
211 #define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_M GENMASK(31, 20)
212 #define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_X(x) (((x) & GENMASK(31, 20)) >> 20)
213 #define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY(x) (((x) << 8) & GENMASK(19, 8))
214 #define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_M GENMASK(19, 8)
215 #define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_X(x) (((x) & GENMASK(19, 8)) >> 8)
216 #define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY(x) ((x) & GENMASK(7, 0))
217 #define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY_M GENMASK(7, 0)
219 #define ICPU_MEMCTRL_MR0_VAL 0x158
221 #define ICPU_MEMCTRL_MR1_VAL 0x15c
223 #define ICPU_MEMCTRL_MR2_VAL 0x160
225 #define ICPU_MEMCTRL_MR3_VAL 0x164
227 #define ICPU_MEMCTRL_TERMRES_CTRL 0x168
229 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
230 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
231 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
232 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
233 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
234 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
235 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
236 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
237 #define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
238 #define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
240 #define ICPU_MEMCTRL_DFT 0x16c
242 #define ICPU_MEMCTRL_DFT_DDRDFT_LBW BIT(7)
243 #define ICPU_MEMCTRL_DFT_DDRDFT_GATE_ENA BIT(6)
244 #define ICPU_MEMCTRL_DFT_DDRDFT_TERM_ENA BIT(5)
245 #define ICPU_MEMCTRL_DFT_DDRDFT_A10 BIT(4)
246 #define ICPU_MEMCTRL_DFT_DDRDFT_STAT BIT(3)
247 #define ICPU_MEMCTRL_DFT_DDRDFT_MODE(x) (((x) << 1) & GENMASK(2, 1))
248 #define ICPU_MEMCTRL_DFT_DDRDFT_MODE_M GENMASK(2, 1)
249 #define ICPU_MEMCTRL_DFT_DDRDFT_MODE_X(x) (((x) & GENMASK(2, 1)) >> 1)
250 #define ICPU_MEMCTRL_DFT_DDRDFT_ENA BIT(0)
252 #define ICPU_MEMCTRL_DQS_DLY(x) (0x170 + 0x4 * (x))
253 #define ICPU_MEMCTRL_DQS_DLY_RSZ 0x4
255 #define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
256 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
257 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
258 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
259 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
260 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
261 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
262 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
263 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
265 #define ICPU_MEMCTRL_DQS_AUTO (0x178 + 0x4 * (x))
266 #define ICPU_MEMCTRL_DQS_AUTO_RSZ 0x4
268 #define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT(x) (((x) << 6) & GENMASK(7, 6))
269 #define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_M GENMASK(7, 6)
270 #define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_X(x) (((x) & GENMASK(7, 6)) >> 6)
271 #define ICPU_MEMCTRL_DQS_AUTO_DQS_OVERFLOW BIT(5)
272 #define ICPU_MEMCTRL_DQS_AUTO_DQS_UNDERFLOW BIT(4)
273 #define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_SRC BIT(3)
274 #define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_UP BIT(2)
275 #define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_DOWN BIT(1)
276 #define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_ENA BIT(0)
278 #define ICPU_MEMPHY_CFG 0x180
280 #define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
281 #define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
282 #define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
283 #define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
284 #define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
285 #define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
286 #define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
287 #define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
288 #define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
289 #define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
290 #define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
292 #define ICPU_MEMPHY_ZCAL 0x1a8
294 #define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
295 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
296 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
297 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
298 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
299 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
300 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
301 #define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
303 #define ICPU_MEMPHY_ZCAL_STAT 0x1ac
305 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12))
306 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12)
307 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12)
308 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8))
309 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8)
310 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8)
311 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6))
312 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6)
313 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6)
314 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4))
315 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4)
316 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4)
317 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2))
318 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2)
319 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2)
320 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1)
321 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0)
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