arch/mips/mach-ath79/ar934x/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Marek Vasut <marex@denx.de>
   4  *
   5  * Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/addrspace.h>
  11 #include <asm/types.h>
  12 #include <linux/bitops.h>
  13 #include <linux/delay.h>
  14 #include <mach/ar71xx_regs.h>
  15 #include <mach/ath79.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 enum {
  20         AR934X_SDRAM = 0,
  21         AR934X_DDR1,
  22         AR934X_DDR2,
  23 };
  24
  25 struct ar934x_mem_config {
  26         u32     config1;
  27         u32     config2;
  28         u32     mode;
  29         u32     extmode;
  30         u32     tap;
  31 };
  32
  33 static const struct ar934x_mem_config ar934x_mem_config[] = {
  34         [AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
  35         [AR934X_DDR1]  = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
  36         [AR934X_DDR2]  = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
  37 };
  38
  39 void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
  40 {
  41         void __iomem *ddr_regs;
  42         const struct ar934x_mem_config *memcfg;
  43         int memtype;
  44         u32 reg, cycle, ctl;
  45
  46         ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
  47                                MAP_NOCACHE);
  48
  49         reg = ath79_get_bootstrap();
  50         if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) {    /* DDR */
  51                 if (reg & AR934X_BOOTSTRAP_DDR1) {      /* DDR 1 */
  52                         memtype = AR934X_DDR1;
  53                         cycle = 0xffff;
  54                 } else {                                /* DDR 2 */
  55                         memtype = AR934X_DDR2;
  56                         if (gd->arch.rev) {
  57                                 ctl = BIT(6);   /* Undocumented bit :-( */
  58                                 if (reg & BIT(3))
  59                                         cycle = 0xff;
  60                                 else
  61                                         cycle = 0xffff;
  62                         } else {
  63                                 /* Force DDR2/x16 configuratio on old chips. */
  64                                 ctl = 0;
  65                                 cycle = 0xffff;         /* DDR2 16bit */
  66                         }
  67
  68                         writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);
  69                         udelay(100);
  70
  71                         writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);
  72                         udelay(10);
  73
  74                         writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);
  75                         udelay(10);
  76
  77                         writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF);
  78                         udelay(10);
  79                 }
  80         } else {                                        /* SDRAM */
  81                 memtype = AR934X_SDRAM;
  82                 cycle = 0xffffffff;
  83
  84                 writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);
  85                 udelay(100);
  86
  87                 /* Undocumented register */
  88                 writel(0x13b, ddr_regs + 0x118);
  89                 udelay(100);
  90         }
  91
  92         memcfg = &ar934x_mem_config[memtype];
  93
  94         writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);
  95         udelay(100);
  96
  97         writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);
  98         udelay(100);
  99
 100         writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
 101         udelay(10);
 102
 103         writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);
 104         mdelay(1);
 105
 106         writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
 107         udelay(10);
 108
 109         if (memtype == AR934X_DDR2) {
 110                 writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);
 111                 udelay(100);
 112
 113                 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
 114                 udelay(10);
 115         }
 116
 117         if (memtype != AR934X_SDRAM)
 118                 writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);
 119
 120         udelay(100);
 121
 122         writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
 123         udelay(10);
 124
 125         writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
 126         udelay(10);
 127
 128         writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);
 129         udelay(100);
 130
 131         writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
 132         udelay(10);
 133
 134         writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);
 135         udelay(100);
 136
 137         writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);
 138         writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);
 139
 140         if (memtype != AR934X_SDRAM) {
 141                 if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) {
 142                         writel(memcfg->tap,
 143                                ddr_regs + AR934X_DDR_REG_TAP_CTRL2);
 144                         writel(memcfg->tap,
 145                                ddr_regs + AR934X_DDR_REG_TAP_CTRL3);
 146                 }
 147         }
 148
 149         writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);
 150         udelay(100);
 151
 152         writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);
 153         udelay(100);
 154
 155         writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);
 156         udelay(100);
 157
 158         writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);
 159         udelay(100);
 160 }
 161
 162 void ddr_tap_tuning(void)
 163 {
 164 }