1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
7 #include <clock_legacy.h>
11 #include <asm/addrspace.h>
12 #include <asm/types.h>
13 #include <linux/bitops.h>
14 #include <linux/delay.h>
15 #include <mach/ar71xx_regs.h>
16 #include <mach/ath79.h>
19 DECLARE_GLOBAL_DATA_PTR;
22 * The math for calculating PLL:
24 * NINT + -------------
25 * XTAL [MHz] 2^(18 - 1)
26 * PLL [MHz] = ------------ * ----------------------
29 * Unfortunatelly, there is no way to reliably compute the variables.
30 * The vendor U-Boot port contains macros for various combinations of
31 * CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern
34 struct ar934x_pll_config {
38 /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
42 struct ar934x_clock_config {
47 struct ar934x_pll_config cpu_pll;
48 struct ar934x_pll_config ddr_pll;
51 static const struct ar934x_clock_config ar934x_clock_config[] = {
52 { 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } },
53 { 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
54 { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
55 { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
56 { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
57 { 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
58 { 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
59 { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
60 { 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
61 { 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
62 { 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
63 { 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } },
64 { 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } },
65 { 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
66 { 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
67 { 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } },
68 { 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
69 { 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
70 { 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
71 { 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } },
72 { 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
73 { 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } },
74 { 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } },
75 { 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } },
76 { 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } },
77 { 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
78 { 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
79 { 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
82 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val)
86 writel(0x10810f00, pll_reg_base + 0x4);
87 writel(srif_val, pll_reg_base + 0x0);
88 writel(0xd0810f00, pll_reg_base + 0x4);
89 writel(0x03000000, pll_reg_base + 0x8);
90 writel(0xd0800f00, pll_reg_base + 0x4);
92 clrbits_be32(pll_reg_base + 0x8, BIT(30));
94 setbits_be32(pll_reg_base + 0x8, BIT(30));
97 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0);
99 clrbits_be32(pll_reg_base + 0x8, BIT(30));
102 /* Check if CPU SRIF PLL locked. */
103 reg = readl(pll_reg_base + 0x8);
104 reg = (reg & 0x7ffff8) >> 3;
105 } while (reg >= 0x40000);
108 void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
110 void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE,
111 AR934X_SRIF_SIZE, MAP_NOCACHE);
112 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
113 AR71XX_PLL_SIZE, MAP_NOCACHE);
114 const struct ar934x_pll_config *pll_cfg;
115 int i, pll_nint, pll_refdiv, xtal_40 = 0;
116 u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif;
118 /* Configure SRIF PLL with initial values. */
119 writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG);
120 writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG);
121 writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG);
122 writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG);
123 writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
125 /* Test for 40MHz XTAL */
126 reg = ath79_get_bootstrap();
127 if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
129 cpu_srif = 0x41c00000;
130 ddr_srif = 0x41680000;
133 cpu_srif = 0x29c00000;
134 ddr_srif = 0x29680000;
137 /* Locate CPU/DDR PLL configuration */
138 for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) {
139 if (cpu_mhz != ar934x_clock_config[i].cpu_freq)
141 if (ddr_mhz != ar934x_clock_config[i].ddr_freq)
143 if (ahb_mhz != ar934x_clock_config[i].ahb_freq)
147 pll_cfg = &ar934x_clock_config[i].cpu_pll;
148 pll_nint = pll_cfg->nint[xtal_40];
149 pll_refdiv = pll_cfg->refdiv;
151 (pll_nint << AR934X_PLL_CPU_CONFIG_NINT_SHIFT) |
152 (pll_refdiv << AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) |
153 (pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) |
154 (pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT);
156 pll_cfg = &ar934x_clock_config[i].ddr_pll;
157 pll_nint = pll_cfg->nint[xtal_40];
158 pll_refdiv = pll_cfg->refdiv;
160 (pll_nint << AR934X_PLL_DDR_CONFIG_NINT_SHIFT) |
161 (pll_refdiv << AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) |
162 (pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) |
163 (pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT);
167 /* PLL configuration not found, hang. */
168 if (i == ARRAY_SIZE(ar934x_clock_config))
172 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
173 AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
174 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
175 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
176 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
177 AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
179 /* Configure CPU PLL */
180 writel(cpu_pll | AR934X_PLL_CPU_CONFIG_PLLPWD,
181 pll_regs + AR934X_PLL_CPU_CONFIG_REG);
182 /* Configure DDR PLL */
183 writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD,
184 pll_regs + AR934X_PLL_DDR_CONFIG_REG);
185 /* Configure PLL routing */
186 writel(AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS |
187 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS |
188 AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS |
189 (0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) |
190 (0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) |
191 (1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) |
192 AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL |
193 AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL |
194 AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL,
195 pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
197 /* Configure SRIF PLLs, which is completely undocumented :-) */
198 ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif);
199 ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif);
201 /* Unset PLL Bypass */
202 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
203 AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
204 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
205 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
206 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
207 AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
209 /* Enable PLL dithering */
210 writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) |
211 (0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT),
212 pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG);
213 writel(48 << AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT,
214 pll_regs + AR934X_PLL_CPU_DIT_FRAC_REG);
217 static u32 ar934x_get_xtal(void)
221 val = ath79_get_bootstrap();
222 if (val & AR934X_BOOTSTRAP_REF_CLK_40)
228 int get_serial_clock(void)
230 return ar934x_get_xtal();
233 static u32 ar934x_cpupll_to_hz(const u32 regval)
235 const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
236 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
237 const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
238 AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
239 const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
240 AR934X_PLL_CPU_CONFIG_NINT_MASK;
241 const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
242 AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
243 const u32 xtal = ar934x_get_xtal();
245 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
248 static u32 ar934x_ddrpll_to_hz(const u32 regval)
250 const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
251 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
252 const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
253 AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
254 const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
255 AR934X_PLL_DDR_CONFIG_NINT_MASK;
256 const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
257 AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
258 const u32 xtal = ar934x_get_xtal();
260 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
263 static void ar934x_update_clock(void)
266 u32 ctrl, cpu, cpupll, ddr, ddrpll;
267 u32 cpudiv, ddrdiv, busdiv;
268 u32 cpuclk, ddrclk, busclk;
270 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
273 cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG);
274 ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG);
275 ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
277 cpupll = ar934x_cpupll_to_hz(cpu);
278 ddrpll = ar934x_ddrpll_to_hz(ddr);
280 if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
281 cpuclk = ar934x_get_xtal();
282 else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
287 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
288 ddrclk = ar934x_get_xtal();
289 else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
294 if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
295 busclk = ar934x_get_xtal();
296 else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
301 cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
302 AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
303 ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
304 AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
305 busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
306 AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
308 gd->cpu_clk = cpuclk / (cpudiv + 1);
309 gd->mem_clk = ddrclk / (ddrdiv + 1);
310 gd->bus_clk = busclk / (busdiv + 1);
313 ulong get_bus_freq(ulong dummy)
315 ar934x_update_clock();
319 ulong get_ddr_freq(ulong dummy)
321 ar934x_update_clock();
325 int do_ar934x_showclk(struct cmd_tbl *cmdtp, int flag, int argc,
328 ar934x_update_clock();
329 printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000);
330 printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000);
331 printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000);
336 clocks, CONFIG_SYS_MAXARGS, 1, do_ar934x_showclk,