1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 #include <linux/delay.h>
12 #include <asm/timer.h>
13 #include <asm/immap.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 static ulong timestamp;
20 #if defined(CONFIG_SLTTMR)
21 #ifndef CONFIG_SYS_UDELAY_BASE
22 # error "uDelay base not defined!"
25 #if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
26 # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
28 extern void dtimer_intr_setup(void);
30 void __udelay(unsigned long usec)
32 slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
36 freq = CONFIG_SYS_TIMER_PRESCALER;
39 out_be32(&timerp->cr, 0);
40 out_be32(&timerp->tcnt, usec * freq);
41 out_be32(&timerp->cr, SLT_CR_TEN);
43 now = in_be32(&timerp->cnt);
45 now = in_be32(&timerp->cnt);
47 setbits_be32(&timerp->sr, SLT_SR_ST);
48 out_be32(&timerp->cr, 0);
51 void dtimer_interrupt(void *not_used)
53 slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
55 /* check for timer interrupt asserted */
56 if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
57 setbits_be32(&timerp->sr, SLT_SR_ST);
65 slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
70 out_be32(&timerp->cr, 0);
71 out_be32(&timerp->tcnt, 0);
73 out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
75 /* initialize and enable timer interrupt */
76 irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
78 /* Interrupt every ms */
79 out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
83 /* set a period of 1us, set timer mode to restart and
84 enable timer and interrupt */
85 out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
89 ulong get_timer(ulong base)
91 return (timestamp - base);
94 #endif /* CONFIG_SLTTMR */