1 // SPDX-License-Identifier: GPL-2.0+
4 * Josef Baumgartner <josef.baumgartner@telex.de>
8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
11 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
13 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
22 #include <asm/immap.h>
25 #include <linux/delay.h>
28 DECLARE_GLOBAL_DATA_PTR;
31 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
33 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
37 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
39 /* we don't return! */
43 #if defined(CONFIG_DISPLAY_CPUINFO)
44 int print_cpuinfo(void)
46 char buf1[32], buf2[32];
48 printf("CPU: Freescale Coldfire MCF5208\n"
49 " CPU CLK %s MHz BUS CLK %s MHz\n",
50 strmhz(buf1, gd->cpu_clk),
51 strmhz(buf2, gd->bus_clk));
54 #endif /* CONFIG_DISPLAY_CPUINFO */
56 #if defined(CONFIG_WATCHDOG)
57 /* Called by macro WATCHDOG_RESET */
58 void watchdog_reset(void)
60 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
62 out_be16(&wdt->sr, 0x5555);
63 out_be16(&wdt->sr, 0xaaaa);
66 int watchdog_disable(void)
68 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
70 /* reset watchdog counter */
71 out_be16(&wdt->sr, 0x5555);
72 out_be16(&wdt->sr, 0xaaaa);
73 /* disable watchdog timer */
74 out_be16(&wdt->cr, 0);
76 puts("WATCHDOG:disabled\n");
80 int watchdog_init(void)
82 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
84 /* disable watchdog */
85 out_be16(&wdt->cr, 0);
87 /* set timeout and enable watchdog */
89 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
91 /* reset watchdog counter */
92 out_be16(&wdt->sr, 0x5555);
93 out_be16(&wdt->sr, 0xaaaa);
95 puts("WATCHDOG:enabled\n");
98 #endif /* #ifdef CONFIG_WATCHDOG */
99 #endif /* #ifdef CONFIG_M5208 */
102 #if defined(CONFIG_DISPLAY_CPUINFO)
104 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
105 * determine which one we are running on, based on the Chip Identification
108 int print_cpuinfo(void)
111 unsigned short cir; /* Chip Identification Register */
112 unsigned short pin; /* Part identification number */
113 unsigned char prn; /* Part revision number */
116 cir = mbar_readShort(MCF_CCM_CIR);
117 pin = cir >> MCF_CCM_CIR_PIN_LEN;
118 prn = cir & MCF_CCM_CIR_PRN_MASK;
121 case MCF_CCM_CIR_PIN_MCF5270:
124 case MCF_CCM_CIR_PIN_MCF5271:
133 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
134 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
136 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
137 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
138 pin, prn, strmhz(buf, CONFIG_SYS_CLK));
142 #endif /* CONFIG_DISPLAY_CPUINFO */
144 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
146 /* Call the board specific reset actions first. */
151 mbar_writeByte(MCF_RCM_RCR,
152 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
156 #if defined(CONFIG_WATCHDOG)
157 void watchdog_reset(void)
159 mbar_writeShort(MCF_WTM_WSR, 0x5555);
160 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
163 int watchdog_disable(void)
165 mbar_writeShort(MCF_WTM_WCR, 0);
169 int watchdog_init(void)
171 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
174 #endif /* #ifdef CONFIG_WATCHDOG */
179 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
181 wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
183 out_be16(&wdp->wdog_wrrr, 0);
186 /* enable watchdog, set timeout to 0 and wait */
187 out_be16(&wdp->wdog_wrrr, 1);
190 /* we don't return! */
194 #if defined(CONFIG_DISPLAY_CPUINFO)
195 int print_cpuinfo(void)
197 sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
202 msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
212 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
217 printf("Freescale MCF5272 %s\n", suf);
220 #endif /* CONFIG_DISPLAY_CPUINFO */
222 #if defined(CONFIG_WATCHDOG)
223 /* Called by macro WATCHDOG_RESET */
224 void watchdog_reset(void)
226 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
228 out_be16(&wdt->wdog_wcr, 0);
231 int watchdog_disable(void)
233 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
235 /* reset watchdog counter */
236 out_be16(&wdt->wdog_wcr, 0);
237 /* disable watchdog interrupt */
238 out_be16(&wdt->wdog_wirr, 0);
239 /* disable watchdog timer */
240 out_be16(&wdt->wdog_wrrr, 0);
242 puts("WATCHDOG:disabled\n");
246 int watchdog_init(void)
248 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
250 /* disable watchdog interrupt */
251 out_be16(&wdt->wdog_wirr, 0);
253 /* set timeout and enable watchdog */
254 out_be16(&wdt->wdog_wrrr,
255 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
257 /* reset watchdog counter */
258 out_be16(&wdt->wdog_wcr, 0);
260 puts("WATCHDOG:enabled\n");
263 #endif /* #ifdef CONFIG_WATCHDOG */
265 #endif /* #ifdef CONFIG_M5272 */
268 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
270 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
274 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
276 /* we don't return! */
280 #if defined(CONFIG_DISPLAY_CPUINFO)
281 int print_cpuinfo(void)
285 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
286 strmhz(buf, CONFIG_SYS_CLK));
289 #endif /* CONFIG_DISPLAY_CPUINFO */
291 #if defined(CONFIG_WATCHDOG)
292 /* Called by macro WATCHDOG_RESET */
293 void watchdog_reset(void)
295 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
297 out_be16(&wdt->wsr, 0x5555);
298 out_be16(&wdt->wsr, 0xaaaa);
301 int watchdog_disable(void)
303 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
305 /* reset watchdog counter */
306 out_be16(&wdt->wsr, 0x5555);
307 out_be16(&wdt->wsr, 0xaaaa);
309 /* disable watchdog timer */
310 out_be16(&wdt->wcr, 0);
312 puts("WATCHDOG:disabled\n");
316 int watchdog_init(void)
318 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
320 /* disable watchdog */
321 out_be16(&wdt->wcr, 0);
323 /* set timeout and enable watchdog */
325 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
327 /* reset watchdog counter */
328 out_be16(&wdt->wsr, 0x5555);
329 out_be16(&wdt->wsr, 0xaaaa);
331 puts("WATCHDOG:enabled\n");
334 #endif /* #ifdef CONFIG_WATCHDOG */
336 #endif /* #ifdef CONFIG_M5275 */
339 #if defined(CONFIG_DISPLAY_CPUINFO)
340 int print_cpuinfo(void)
342 unsigned char resetsource = MCFRESET_RSR;
344 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
345 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
346 printf("Reset:%s%s%s%s%s%s%s\n",
347 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
348 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
349 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
350 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
351 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
352 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
353 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
356 #endif /* CONFIG_DISPLAY_CPUINFO */
358 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
360 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
366 #if defined(CONFIG_DISPLAY_CPUINFO)
367 int print_cpuinfo(void)
371 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
372 strmhz(buf, CONFIG_SYS_CLK));
375 #endif /* CONFIG_DISPLAY_CPUINFO */
377 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
379 /* enable watchdog, set timeout to 0 and wait */
380 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
383 /* we don't return! */
389 #if defined(CONFIG_DISPLAY_CPUINFO)
390 int print_cpuinfo(void)
394 unsigned char resetsource = mbar_readLong(SIM_RSR);
395 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
396 strmhz(buf, CONFIG_SYS_CLK));
398 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
399 printf("Reset:%s%s\n",
400 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
402 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
407 #endif /* CONFIG_DISPLAY_CPUINFO */
409 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
411 /* enable watchdog, set timeout to 0 and wait */
412 mbar_writeByte(SIM_SYPCR, 0xc0);
415 /* we don't return! */
420 #if defined(CONFIG_MCFFEC)
421 /* Default initializations for MCFFEC controllers. To override,
422 * create a board-specific function called:
423 * int board_eth_init(bd_t *bis)
426 int cpu_eth_init(bd_t *bis)
428 return mcffec_initialize(bis);