arch/arm/mach-zynqmp/mp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <log.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/io.h>
  13 #include <linux/delay.h>
  14
  15 #define LOCK            0
  16 #define SPLIT           1
  17
  18 #define HALT            0
  19 #define RELEASE         1
  20
  21 #define ZYNQMP_BOOTADDR_HIGH_MASK               0xFFFFFFFF
  22 #define ZYNQMP_R5_HIVEC_ADDR                    0xFFFF0000
  23 #define ZYNQMP_R5_LOVEC_ADDR                    0x0
  24 #define ZYNQMP_RPU_CFG_CPU_HALT_MASK            0x01
  25 #define ZYNQMP_RPU_CFG_HIVEC_MASK               0x04
  26 #define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK    0x08
  27 #define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK      0x40
  28 #define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK       0x10
  29
  30 #define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK     0x04
  31 #define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK      0x01
  32 #define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK      0x02
  33 #define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK   0x1000000
  34
  35 #define ZYNQMP_TCM_START_ADDRESS                0xFFE00000
  36 #define ZYNQMP_TCM_BOTH_SIZE                    0x40000
  37
  38 #define ZYNQMP_CORE_APU0        0
  39 #define ZYNQMP_CORE_APU3        3
  40
  41 #define ZYNQMP_MAX_CORES        6
  42
  43 int is_core_valid(unsigned int core)
  44 {
  45         if (core < ZYNQMP_MAX_CORES)
  46                 return 1;
  47
  48         return 0;
  49 }
  50
  51 int cpu_reset(u32 nr)
  52 {
  53         puts("Feature is not implemented.\n");
  54         return 0;
  55 }
  56
  57 static void set_r5_halt_mode(u8 halt, u8 mode)
  58 {
  59         u32 tmp;
  60
  61         tmp = readl(&rpu_base->rpu0_cfg);
  62         if (halt == HALT)
  63                 tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  64         else
  65                 tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  66         writel(tmp, &rpu_base->rpu0_cfg);
  67
  68         if (mode == LOCK) {
  69                 tmp = readl(&rpu_base->rpu1_cfg);
  70                 if (halt == HALT)
  71                         tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  72                 else
  73                         tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  74                 writel(tmp, &rpu_base->rpu1_cfg);
  75         }
  76 }
  77
  78 static void set_r5_tcm_mode(u8 mode)
  79 {
  80         u32 tmp;
  81
  82         tmp = readl(&rpu_base->rpu_glbl_ctrl);
  83         if (mode == LOCK) {
  84                 tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  85                 tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
  86                        ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK;
  87         } else {
  88                 tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  89                 tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
  90                        ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK);
  91         }
  92
  93         writel(tmp, &rpu_base->rpu_glbl_ctrl);
  94 }
  95
  96 static void set_r5_reset(u8 mode)
  97 {
  98         u32 tmp;
  99
 100         tmp = readl(&crlapb_base->rst_lpd_top);
 101         tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
 102                ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
 103
 104         if (mode == LOCK)
 105                 tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
 106
 107         writel(tmp, &crlapb_base->rst_lpd_top);
 108 }
 109
 110 static void release_r5_reset(u8 mode)
 111 {
 112         u32 tmp;
 113
 114         tmp = readl(&crlapb_base->rst_lpd_top);
 115         tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
 116                ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
 117
 118         if (mode == LOCK)
 119                 tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
 120
 121         writel(tmp, &crlapb_base->rst_lpd_top);
 122 }
 123
 124 static void enable_clock_r5(void)
 125 {
 126         u32 tmp;
 127
 128         tmp = readl(&crlapb_base->cpu_r5_ctrl);
 129         tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
 130         writel(tmp, &crlapb_base->cpu_r5_ctrl);
 131
 132         /* Give some delay for clock
 133          * to propagate */
 134         udelay(0x500);
 135 }
 136
 137 int cpu_disable(u32 nr)
 138 {
 139         if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
 140                 u32 val = readl(&crfapb_base->rst_fpd_apu);
 141                 val |= 1 << nr;
 142                 writel(val, &crfapb_base->rst_fpd_apu);
 143         } else {
 144                 set_r5_reset(LOCK);
 145         }
 146
 147         return 0;
 148 }
 149
 150 int cpu_status(u32 nr)
 151 {
 152         if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
 153                 u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
 154                 u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) +
 155                                       nr * 8);
 156                 u32 val = readl(&crfapb_base->rst_fpd_apu);
 157                 val &= 1 << nr;
 158                 printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n",
 159                        nr, val ? "OFF" : "ON" , addr_high, addr_low);
 160         } else {
 161                 u32 val = readl(&crlapb_base->rst_lpd_top);
 162                 val &= 1 << (nr - 4);
 163                 printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON");
 164         }
 165
 166         return 0;
 167 }
 168
 169 static void set_r5_start(u8 high)
 170 {
 171         u32 tmp;
 172
 173         tmp = readl(&rpu_base->rpu0_cfg);
 174         if (high)
 175                 tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
 176         else
 177                 tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
 178         writel(tmp, &rpu_base->rpu0_cfg);
 179
 180         tmp = readl(&rpu_base->rpu1_cfg);
 181         if (high)
 182                 tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
 183         else
 184                 tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
 185         writel(tmp, &rpu_base->rpu1_cfg);
 186 }
 187
 188 static void write_tcm_boot_trampoline(u32 boot_addr)
 189 {
 190         if (boot_addr) {
 191                 /*
 192                  * Boot trampoline is simple ASM code below.
 193                  *
 194                  *              b over;
 195                  *      label:
 196                  *      .word   0
 197                  *      over:   ldr     r0, =label
 198                  *              ldr     r1, [r0]
 199                  *              bx      r1
 200                  */
 201                 debug("Write boot trampoline for %x\n", boot_addr);
 202                 writel(0xea000000, ZYNQMP_TCM_START_ADDRESS);
 203                 writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4);
 204                 writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8);
 205                 writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc);
 206                 writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10);
 207                 writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for
 208         }
 209 }
 210
 211 void initialize_tcm(bool mode)
 212 {
 213         if (!mode) {
 214                 set_r5_tcm_mode(LOCK);
 215                 set_r5_halt_mode(HALT, LOCK);
 216                 enable_clock_r5();
 217                 release_r5_reset(LOCK);
 218         } else {
 219                 set_r5_tcm_mode(SPLIT);
 220                 set_r5_halt_mode(HALT, SPLIT);
 221                 enable_clock_r5();
 222                 release_r5_reset(SPLIT);
 223         }
 224 }
 225
 226 int cpu_release(u32 nr, int argc, char *const argv[])
 227 {
 228         if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
 229                 u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
 230                 /* HIGH */
 231                 writel((u32)(boot_addr >> 32),
 232                        ((u8 *)&apu_base->rvbar_addr0_h) + nr * 8);
 233                 /* LOW */
 234                 writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK),
 235                        ((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
 236
 237                 u32 val = readl(&crfapb_base->rst_fpd_apu);
 238                 val &= ~(1 << nr);
 239                 writel(val, &crfapb_base->rst_fpd_apu);
 240         } else {
 241                 if (argc != 2) {
 242                         printf("Invalid number of arguments to release.\n");
 243                         printf("<addr> <mode>-Start addr lockstep or split\n");
 244                         return 1;
 245                 }
 246
 247                 u32 boot_addr = simple_strtoul(argv[0], NULL, 16);
 248                 u32 boot_addr_uniq = 0;
 249                 if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR ||
 250                       boot_addr == ZYNQMP_R5_HIVEC_ADDR)) {
 251                         printf("Using TCM jump trampoline for address 0x%x\n",
 252                                boot_addr);
 253                         /* Save boot address for later usage */
 254                         boot_addr_uniq = boot_addr;
 255                         /*
 256                          * R5 needs to start from LOVEC at TCM
 257                          * OCM will be probably occupied by ATF
 258                          */
 259                         boot_addr = ZYNQMP_R5_LOVEC_ADDR;
 260                 }
 261
 262                 /*
 263                  * Since we don't know where the user may have loaded the image
 264                  * for an R5 we have to flush all the data cache to ensure
 265                  * the R5 sees it.
 266                  */
 267                 flush_dcache_all();
 268
 269                 if (!strncmp(argv[1], "lockstep", 8)) {
 270                         printf("R5 lockstep mode\n");
 271                         set_r5_reset(LOCK);
 272                         set_r5_tcm_mode(LOCK);
 273                         set_r5_halt_mode(HALT, LOCK);
 274                         set_r5_start(boot_addr);
 275                         enable_clock_r5();
 276                         release_r5_reset(LOCK);
 277                         dcache_disable();
 278                         write_tcm_boot_trampoline(boot_addr_uniq);
 279                         dcache_enable();
 280                         set_r5_halt_mode(RELEASE, LOCK);
 281                 } else if (!strncmp(argv[1], "split", 5)) {
 282                         printf("R5 split mode\n");
 283                         set_r5_reset(SPLIT);
 284                         set_r5_tcm_mode(SPLIT);
 285                         set_r5_halt_mode(HALT, SPLIT);
 286                         set_r5_start(boot_addr);
 287                         enable_clock_r5();
 288                         release_r5_reset(SPLIT);
 289                         dcache_disable();
 290                         write_tcm_boot_trampoline(boot_addr_uniq);
 291                         dcache_enable();
 292                         set_r5_halt_mode(RELEASE, SPLIT);
 293                 } else {
 294                         printf("Unsupported mode\n");
 295                         return 1;
 296                 }
 297         }
 298
 299         return 0;
 300 }