arch/arm/mach-zynqmp/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <time.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/armv8/mmu.h>
  13 #include <asm/cache.h>
  14 #include <asm/io.h>
  15 #include <zynqmp_firmware.h>
  16 #include <asm/cache.h>
  17
  18 #define ZYNQ_SILICON_VER_MASK   0xF000
  19 #define ZYNQ_SILICON_VER_SHIFT  12
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 /*
  24  * Number of filled static entries and also the first empty
  25  * slot in zynqmp_mem_map.
  26  */
  27 #define ZYNQMP_MEM_MAP_USED     4
  28
  29 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  30 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  31 #else
  32 #define DRAM_BANKS 0
  33 #endif
  34
  35 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  36 #define TCM_MAP 1
  37 #else
  38 #define TCM_MAP 0
  39 #endif
  40
  41 /* +1 is end of list which needs to be empty */
  42 #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  43
  44 static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
  45         {
  46                 .virt = 0x80000000UL,
  47                 .phys = 0x80000000UL,
  48                 .size = 0x70000000UL,
  49                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  50                          PTE_BLOCK_NON_SHARE |
  51                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  52         }, {
  53                 .virt = 0xf8000000UL,
  54                 .phys = 0xf8000000UL,
  55                 .size = 0x07e00000UL,
  56                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  57                          PTE_BLOCK_NON_SHARE |
  58                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  59         }, {
  60                 .virt = 0x400000000UL,
  61                 .phys = 0x400000000UL,
  62                 .size = 0x400000000UL,
  63                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  64                          PTE_BLOCK_NON_SHARE |
  65                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  66         }, {
  67                 .virt = 0x1000000000UL,
  68                 .phys = 0x1000000000UL,
  69                 .size = 0xf000000000UL,
  70                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  71                          PTE_BLOCK_NON_SHARE |
  72                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  73         }
  74 };
  75
  76 void mem_map_fill(void)
  77 {
  78         int banks = ZYNQMP_MEM_MAP_USED;
  79
  80 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  81         zynqmp_mem_map[banks].virt = 0xffe00000UL;
  82         zynqmp_mem_map[banks].phys = 0xffe00000UL;
  83         zynqmp_mem_map[banks].size = 0x00200000UL;
  84         zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  85                                       PTE_BLOCK_INNER_SHARE;
  86         banks = banks + 1;
  87 #endif
  88
  89 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  90         for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  91                 /* Zero size means no more DDR that's this is end */
  92                 if (!gd->bd->bi_dram[i].size)
  93                         break;
  94
  95                 zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  96                 zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  97                 zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
  98                 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  99                                               PTE_BLOCK_INNER_SHARE;
 100                 banks = banks + 1;
 101         }
 102 #endif
 103 }
 104
 105 struct mm_region *mem_map = zynqmp_mem_map;
 106
 107 u64 get_page_table_size(void)
 108 {
 109         return 0x14000;
 110 }
 111
 112 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
 113 void tcm_init(u8 mode)
 114 {
 115         puts("WARNING: Initializing TCM overwrites TCM content\n");
 116         initialize_tcm(mode);
 117         memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
 118 }
 119 #endif
 120
 121 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
 122 int arm_reserve_mmu(void)
 123 {
 124         tcm_init(TCM_LOCK);
 125         gd->arch.tlb_size = PGTABLE_SIZE;
 126         gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
 127
 128         return 0;
 129 }
 130 #endif
 131
 132 static unsigned int zynqmp_get_silicon_version_secure(void)
 133 {
 134         u32 ver;
 135
 136         ver = readl(&csu_base->version);
 137         ver &= ZYNQMP_SILICON_VER_MASK;
 138         ver >>= ZYNQMP_SILICON_VER_SHIFT;
 139
 140         return ver;
 141 }
 142
 143 unsigned int zynqmp_get_silicon_version(void)
 144 {
 145         if (current_el() == 3)
 146                 return zynqmp_get_silicon_version_secure();
 147
 148         gd->cpu_clk = get_tbclk();
 149
 150         switch (gd->cpu_clk) {
 151         case 50000000:
 152                 return ZYNQMP_CSU_VERSION_QEMU;
 153         }
 154
 155         return ZYNQMP_CSU_VERSION_SILICON;
 156 }
 157
 158 static int zynqmp_mmio_rawwrite(const u32 address,
 159                       const u32 mask,
 160                       const u32 value)
 161 {
 162         u32 data;
 163         u32 value_local = value;
 164         int ret;
 165
 166         ret = zynqmp_mmio_read(address, &data);
 167         if (ret)
 168                 return ret;
 169
 170         data &= ~mask;
 171         value_local &= mask;
 172         value_local |= data;
 173         writel(value_local, (ulong)address);
 174         return 0;
 175 }
 176
 177 static int zynqmp_mmio_rawread(const u32 address, u32 *value)
 178 {
 179         *value = readl((ulong)address);
 180         return 0;
 181 }
 182
 183 int zynqmp_mmio_write(const u32 address,
 184                       const u32 mask,
 185                       const u32 value)
 186 {
 187         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
 188                 return zynqmp_mmio_rawwrite(address, mask, value);
 189 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 190         else
 191                 return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
 192                                          value, 0, NULL);
 193 #endif
 194
 195         return -EINVAL;
 196 }
 197
 198 int zynqmp_mmio_read(const u32 address, u32 *value)
 199 {
 200         u32 ret = -EINVAL;
 201
 202         if (!value)
 203                 return ret;
 204
 205         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 206                 ret = zynqmp_mmio_rawread(address, value);
 207         }
 208 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 209         else {
 210                 u32 ret_payload[PAYLOAD_ARG_CNT];
 211
 212                 ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
 213                                         0, ret_payload);
 214                 *value = ret_payload[1];
 215         }
 216 #endif
 217
 218         return ret;
 219 }