arch/arm/mach-versal/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <asm/armv8/mmu.h>
  10 #include <asm/cache.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/cache.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 #define VERSAL_MEM_MAP_USED     5
  19
  20 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  21
  22 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  23 #define TCM_MAP 1
  24 #else
  25 #define TCM_MAP 0
  26 #endif
  27
  28 /* +1 is end of list which needs to be empty */
  29 #define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  30
  31 static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
  32         {
  33                 .virt = 0x80000000UL,
  34                 .phys = 0x80000000UL,
  35                 .size = 0x70000000UL,
  36                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  37                          PTE_BLOCK_NON_SHARE |
  38                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  39         }, {
  40                 .virt = 0xf0000000UL,
  41                 .phys = 0xf0000000UL,
  42                 .size = 0x0fe00000UL,
  43                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  44                          PTE_BLOCK_NON_SHARE |
  45                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  46         }, {
  47                 .virt = 0x400000000UL,
  48                 .phys = 0x400000000UL,
  49                 .size = 0x200000000UL,
  50                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  51                          PTE_BLOCK_NON_SHARE |
  52                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  53         }, {
  54                 .virt = 0x600000000UL,
  55                 .phys = 0x600000000UL,
  56                 .size = 0x800000000UL,
  57                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  58                          PTE_BLOCK_INNER_SHARE
  59         }, {
  60                 .virt = 0xe00000000UL,
  61                 .phys = 0xe00000000UL,
  62                 .size = 0xf200000000UL,
  63                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  64                          PTE_BLOCK_NON_SHARE |
  65                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  66         }
  67 };
  68
  69 void mem_map_fill(void)
  70 {
  71         int banks = VERSAL_MEM_MAP_USED;
  72
  73 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  74         versal_mem_map[banks].virt = 0xffe00000UL;
  75         versal_mem_map[banks].phys = 0xffe00000UL;
  76         versal_mem_map[banks].size = 0x00200000UL;
  77         versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  78                                       PTE_BLOCK_INNER_SHARE;
  79         banks = banks + 1;
  80 #endif
  81
  82         for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  83                 /* Zero size means no more DDR that's this is end */
  84                 if (!gd->bd->bi_dram[i].size)
  85                         break;
  86
  87 #if defined(CONFIG_VERSAL_NO_DDR)
  88                 if (gd->bd->bi_dram[i].start < 0x80000000UL ||
  89                     gd->bd->bi_dram[i].start > 0x100000000UL) {
  90                         printf("Ignore caches over %llx/%llx\n",
  91                                gd->bd->bi_dram[i].start,
  92                                gd->bd->bi_dram[i].size);
  93                         continue;
  94                 }
  95 #endif
  96                 versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  97                 versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  98                 versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
  99                 versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 100                                               PTE_BLOCK_INNER_SHARE;
 101                 banks = banks + 1;
 102         }
 103 }
 104
 105 struct mm_region *mem_map = versal_mem_map;
 106
 107 u64 get_page_table_size(void)
 108 {
 109         return 0x14000;
 110 }
 111
 112 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
 113 int arm_reserve_mmu(void)
 114 {
 115         tcm_init(TCM_LOCK);
 116         gd->arch.tlb_size = PGTABLE_SIZE;
 117         gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR;
 118
 119         return 0;
 120 }
 121 #endif