arch/arm/mach-uniphier/sbc/sbc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2011-2015 Panasonic Corporation
   4  * Copyright (C) 2015-2017 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  */
   7
   8 #include <linux/io.h>
   9 #include <asm/global_data.h>
  10
  11 #include "../init.h"
  12 #include "sbc-regs.h"
  13
  14 #define SBCTRL0_ADMULTIPLX_PERI_VALUE   0x33120000
  15 #define SBCTRL1_ADMULTIPLX_PERI_VALUE   0x03005500
  16 #define SBCTRL2_ADMULTIPLX_PERI_VALUE   0x14000020
  17
  18 #define SBCTRL0_ADMULTIPLX_MEM_VALUE    0x33120000
  19 #define SBCTRL1_ADMULTIPLX_MEM_VALUE    0x03005500
  20 #define SBCTRL2_ADMULTIPLX_MEM_VALUE    0x14000010
  21
  22 /* slower but LED works */
  23 #define SBCTRL0_SAVEPIN_PERI_VALUE      0x55450000
  24 #define SBCTRL1_SAVEPIN_PERI_VALUE      0x07168d00
  25 #define SBCTRL2_SAVEPIN_PERI_VALUE      0x34000009
  26 #define SBCTRL4_SAVEPIN_PERI_VALUE      0x02110110
  27
  28 /* faster but LED does not work */
  29 #define SBCTRL0_SAVEPIN_MEM_VALUE       0x55450000
  30 #define SBCTRL1_SAVEPIN_MEM_VALUE       0x06057700
  31 /* NOR flash needs more wait counts than SRAM */
  32 #define SBCTRL2_SAVEPIN_MEM_VALUE       0x34000009
  33 #define SBCTRL4_SAVEPIN_MEM_VALUE       0x02110210
  34
  35 int uniphier_sbc_is_enabled(void)
  36 {
  37         DECLARE_GLOBAL_DATA_PTR;
  38         const void *fdt = gd->fdt_blob;
  39         int offset;
  40
  41         offset = fdt_node_offset_by_compatible(fdt, 0,
  42                                                "socionext,uniphier-system-bus");
  43         if (offset < 0)
  44                 return 0;
  45
  46         return fdtdec_get_is_enabled(fdt, offset);
  47 }
  48
  49 static void __uniphier_sbc_init(int savepin)
  50 {
  51         /*
  52          * Only CS1 is connected to support card.
  53          * BKSZ[1:0] should be set to "01".
  54          */
  55         if (savepin) {
  56                 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
  57                 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
  58                 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
  59                 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
  60         } else {
  61                 writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
  62                 writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
  63                 writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
  64         }
  65
  66         if (uniphier_sbc_boot_is_swapped()) {
  67                 /*
  68                  * Boot Swap On: boot from external NOR/SRAM
  69                  * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
  70                  *
  71                  * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
  72                  * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
  73                  */
  74                 writel(0x0000bc01, SBBASE0);
  75         } else {
  76                 /*
  77                  * Boot Swap Off: boot from mask ROM
  78                  * 0x40000000-0x41ffffff: mask ROM
  79                  * 0x42000000-0x43efffff: memory bank (31MB)
  80                  * 0x43f00000-0x43ffffff: peripherals (1MB)
  81                  */
  82                 writel(0x0000be01, SBBASE0); /* dummy */
  83                 writel(0x0200be01, SBBASE1);
  84         }
  85 }
  86
  87 void uniphier_sbc_init_admulti(void)
  88 {
  89         __uniphier_sbc_init(0);
  90 }
  91
  92 void uniphier_sbc_init_savepin(void)
  93 {
  94         __uniphier_sbc_init(1);
  95 }