arch/arm/mach-uniphier/dram/cmd_ddrphy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014      Panasonic Corporation
   4  * Copyright (C) 2015-2017 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  */
   7
   8 #include <command.h>
   9 #include <stdio.h>
  10 #include <linux/io.h>
  11 #include <linux/printk.h>
  12 #include <linux/sizes.h>
  13
  14 #include "../soc-info.h"
  15 #include "ddrphy-regs.h"
  16
  17 /* Select either decimal or hexadecimal */
  18 #if 1
  19 #define PRINTF_FORMAT "%2d"
  20 #else
  21 #define PRINTF_FORMAT "%02x"
  22 #endif
  23 /* field separator */
  24 #define FS "   "
  25
  26 #define ptr_to_uint(p)  ((unsigned int)(unsigned long)(p))
  27
  28 #define UNIPHIER_MAX_NR_DDRPHY          4
  29
  30 struct uniphier_ddrphy_param {
  31         unsigned int soc_id;
  32         unsigned int nr_phy;
  33         struct {
  34                 resource_size_t base;
  35                 unsigned int nr_dx;
  36         } phy[UNIPHIER_MAX_NR_DDRPHY];
  37 };
  38
  39 static const struct uniphier_ddrphy_param uniphier_ddrphy_param[] = {
  40         {
  41                 .soc_id = UNIPHIER_LD4_ID,
  42                 .nr_phy = 2,
  43                 .phy = {
  44                         { .base = 0x5bc01000, .nr_dx = 2, },
  45                         { .base = 0x5be01000, .nr_dx = 2, },
  46                 },
  47         },
  48         {
  49                 .soc_id = UNIPHIER_PRO4_ID,
  50                 .nr_phy = 4,
  51                 .phy = {
  52                         { .base = 0x5bc01000, .nr_dx = 2, },
  53                         { .base = 0x5bc02000, .nr_dx = 2, },
  54                         { .base = 0x5be01000, .nr_dx = 2, },
  55                         { .base = 0x5be02000, .nr_dx = 2, },
  56                 },
  57         },
  58         {
  59                 .soc_id = UNIPHIER_SLD8_ID,
  60                 .nr_phy = 2,
  61                 .phy = {
  62                         { .base = 0x5bc01000, .nr_dx = 2, },
  63                         { .base = 0x5be01000, .nr_dx = 2, },
  64                 },
  65         },
  66         {
  67                 .soc_id = UNIPHIER_LD11_ID,
  68                 .nr_phy = 1,
  69                 .phy = {
  70                         { .base = 0x5bc01000, .nr_dx = 4, },
  71                 },
  72         },
  73 };
  74 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrphy_param, uniphier_ddrphy_param)
  75
  76 static void print_bdl(void __iomem *reg, int n)
  77 {
  78         u32 val = readl(reg);
  79         int i;
  80
  81         for (i = 0; i < n; i++)
  82                 printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
  83 }
  84
  85 static void dump_loop(const struct uniphier_ddrphy_param *param,
  86                       void (*callback)(void __iomem *))
  87 {
  88         void __iomem *phy_base, *dx_base;
  89         int phy, dx;
  90
  91         for (phy = 0; phy < param->nr_phy; phy++) {
  92                 phy_base = ioremap(param->phy[phy].base, SZ_4K);
  93                 dx_base = phy_base + PHY_DX_BASE;
  94
  95                 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
  96                         printf("PHY%dDX%d:", phy, dx);
  97                         (*callback)(dx_base);
  98                         dx_base += PHY_DX_STRIDE;
  99                         printf("\n");
 100                 }
 101
 102                 iounmap(phy_base);
 103         }
 104 }
 105
 106 static void __wbdl_dump(void __iomem *dx_base)
 107 {
 108         print_bdl(dx_base + PHY_DX_BDLR0, 5);
 109         print_bdl(dx_base + PHY_DX_BDLR1, 5);
 110
 111         printf(FS "(+" PRINTF_FORMAT ")",
 112                readl(dx_base + PHY_DX_LCDLR1) & 0xff);
 113 }
 114
 115 static void wbdl_dump(const struct uniphier_ddrphy_param *param)
 116 {
 117         printf("\n--- Write Bit Delay Line ---\n");
 118         printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  DQS  (WDQD)\n");
 119
 120         dump_loop(param, &__wbdl_dump);
 121 }
 122
 123 static void __rbdl_dump(void __iomem *dx_base)
 124 {
 125         print_bdl(dx_base + PHY_DX_BDLR3, 5);
 126         print_bdl(dx_base + PHY_DX_BDLR4, 4);
 127
 128         printf(FS "(+" PRINTF_FORMAT ")",
 129                (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
 130 }
 131
 132 static void rbdl_dump(const struct uniphier_ddrphy_param *param)
 133 {
 134         printf("\n--- Read Bit Delay Line ---\n");
 135         printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  (RDQSD)\n");
 136
 137         dump_loop(param, &__rbdl_dump);
 138 }
 139
 140 static void __wld_dump(void __iomem *dx_base)
 141 {
 142         int rank;
 143         u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
 144         u32 gtr = readl(dx_base + PHY_DX_GTR);
 145
 146         for (rank = 0; rank < 4; rank++) {
 147                 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
 148                 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
 149
 150                 printf(FS PRINTF_FORMAT "%sT", wld,
 151                        wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
 152         }
 153 }
 154
 155 static void wld_dump(const struct uniphier_ddrphy_param *param)
 156 {
 157         printf("\n--- Write Leveling Delay ---\n");
 158         printf("           Rank0   Rank1   Rank2   Rank3\n");
 159
 160         dump_loop(param, &__wld_dump);
 161 }
 162
 163 static void __dqsgd_dump(void __iomem *dx_base)
 164 {
 165         int rank;
 166         u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
 167         u32 gtr = readl(dx_base + PHY_DX_GTR);
 168
 169         for (rank = 0; rank < 4; rank++) {
 170                 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
 171                 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
 172
 173                 printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
 174         }
 175 }
 176
 177 static void dqsgd_dump(const struct uniphier_ddrphy_param *param)
 178 {
 179         printf("\n--- DQS Gating Delay ---\n");
 180         printf("           Rank0   Rank1   Rank2   Rank3\n");
 181
 182         dump_loop(param, &__dqsgd_dump);
 183 }
 184
 185 static void __mdl_dump(void __iomem *dx_base)
 186 {
 187         int i;
 188         u32 mdl = readl(dx_base + PHY_DX_MDLR);
 189
 190         for (i = 0; i < 3; i++)
 191                 printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
 192 }
 193
 194 static void mdl_dump(const struct uniphier_ddrphy_param *param)
 195 {
 196         printf("\n--- Master Delay Line ---\n");
 197         printf("          IPRD TPRD MDLD\n");
 198
 199         dump_loop(param, &__mdl_dump);
 200 }
 201
 202 #define REG_DUMP(x)                                                     \
 203         { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst;    \
 204                 printf("%3d: %-10s: %08x : %08x\n",                     \
 205                        ofst >> PHY_REG_SHIFT, #x,                       \
 206                        ptr_to_uint(reg), readl(reg)); }
 207
 208 #define DX_REG_DUMP(dx, x)                                              \
 209         { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) +               \
 210                         PHY_DX_## x;                                    \
 211                 void __iomem *reg = phy_base + ofst;                    \
 212                 printf("%3d: DX%d%-7s: %08x : %08x\n",                  \
 213                        ofst >> PHY_REG_SHIFT, (dx), #x,                 \
 214                        ptr_to_uint(reg), readl(reg)); }
 215
 216 static void reg_dump(const struct uniphier_ddrphy_param *param)
 217 {
 218         void __iomem *phy_base;
 219         int phy, dx;
 220
 221         printf("\n--- DDR PHY registers ---\n");
 222
 223         for (phy = 0; phy < param->nr_phy; phy++) {
 224                 phy_base = ioremap(param->phy[phy].base, SZ_4K);
 225
 226                 printf("== PHY%d (base: %08x) ==\n",
 227                        phy, ptr_to_uint(phy_base));
 228                 printf(" No: Name      : Address  : Data\n");
 229
 230                 REG_DUMP(RIDR);
 231                 REG_DUMP(PIR);
 232                 REG_DUMP(PGCR0);
 233                 REG_DUMP(PGCR1);
 234                 REG_DUMP(PGSR0);
 235                 REG_DUMP(PGSR1);
 236                 REG_DUMP(PLLCR);
 237                 REG_DUMP(PTR0);
 238                 REG_DUMP(PTR1);
 239                 REG_DUMP(PTR2);
 240                 REG_DUMP(PTR3);
 241                 REG_DUMP(PTR4);
 242                 REG_DUMP(ACMDLR);
 243                 REG_DUMP(ACBDLR);
 244                 REG_DUMP(DXCCR);
 245                 REG_DUMP(DSGCR);
 246                 REG_DUMP(DCR);
 247                 REG_DUMP(DTPR0);
 248                 REG_DUMP(DTPR1);
 249                 REG_DUMP(DTPR2);
 250                 REG_DUMP(MR0);
 251                 REG_DUMP(MR1);
 252                 REG_DUMP(MR2);
 253                 REG_DUMP(MR3);
 254
 255                 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
 256                         DX_REG_DUMP(dx, GCR);
 257                         DX_REG_DUMP(dx, GTR);
 258                 }
 259
 260                 iounmap(phy_base);
 261         }
 262 }
 263
 264 static int do_ddr(struct cmd_tbl *cmdtp, int flag, int argc,
 265                   char *const argv[])
 266 {
 267         const struct uniphier_ddrphy_param *param;
 268         char *cmd;
 269
 270         param = uniphier_get_ddrphy_param();
 271         if (!param) {
 272                 pr_err("unsupported SoC\n");
 273                 return CMD_RET_FAILURE;
 274         }
 275
 276         if (argc == 1)
 277                 cmd = "all";
 278         else
 279                 cmd = argv[1];
 280
 281         if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
 282                 wbdl_dump(param);
 283
 284         if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
 285                 rbdl_dump(param);
 286
 287         if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
 288                 wld_dump(param);
 289
 290         if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
 291                 dqsgd_dump(param);
 292
 293         if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
 294                 mdl_dump(param);
 295
 296         if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
 297                 reg_dump(param);
 298
 299         return CMD_RET_SUCCESS;
 300 }
 301
 302 U_BOOT_CMD(
 303         ddr,    2,      1,      do_ddr,
 304         "UniPhier DDR PHY parameters dumper",
 305         "- dump all of the following\n"
 306         "ddr wbdl - dump Write Bit Delay\n"
 307         "ddr rbdl - dump Read Bit Delay\n"
 308         "ddr wld - dump Write Leveling\n"
 309         "ddr dqsgd - dump DQS Gating Delay\n"
 310         "ddr mdl - dump Master Delay Line\n"
 311         "ddr reg - dump registers\n"
 312 );