arch/arm/mach-sunxi/dram_sun6i.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Sun6i platform dram controller init.
   4  *
   5  * (C) Copyright 2007-2012
   6  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   7  * Berg Xing <bergxing@allwinnertech.com>
   8  * Tom Cubie <tangliang@allwinnertech.com>
   9  *
  10  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
  11  */
  12 #include <common.h>
  13 #include <errno.h>
  14 #include <init.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/dram.h>
  18 #include <asm/arch/prcm.h>
  19 #include <linux/delay.h>
  20
  21 #define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
  22
  23 struct dram_sun6i_para {
  24         u8 bus_width;
  25         u8 chan;
  26         u8 rank;
  27         u8 rows;
  28         u16 page_size;
  29 };
  30
  31 static void mctl_sys_init(void)
  32 {
  33         struct sunxi_ccm_reg * const ccm =
  34                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  35         const int dram_clk_div = 2;
  36
  37         clock_set_pll5(DRAM_CLK * dram_clk_div, false);
  38
  39         clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
  40                 CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
  41                 CCM_DRAMCLK_CFG_UPD);
  42         mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
  43
  44         writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
  45
  46         /* deassert mctl reset */
  47         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
  48
  49         /* enable mctl clock */
  50         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
  51 }
  52
  53 static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
  54 {
  55         struct sunxi_mctl_phy_reg *mctl_phy;
  56
  57         if (ch_index == 0)
  58                 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
  59         else
  60                 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
  61
  62         /* disable + reset dlls */
  63         writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr);
  64         writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr);
  65         writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr);
  66         if (para->bus_width == 32) {
  67                 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr);
  68                 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr);
  69         }
  70         udelay(2);
  71
  72         /* enable + reset dlls */
  73         writel(0, &mctl_phy->acdllcr);
  74         writel(0, &mctl_phy->dx0dllcr);
  75         writel(0, &mctl_phy->dx1dllcr);
  76         if (para->bus_width == 32) {
  77                 writel(0, &mctl_phy->dx2dllcr);
  78                 writel(0, &mctl_phy->dx3dllcr);
  79         }
  80         udelay(22);
  81
  82         /* enable and release reset of dlls */
  83         writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr);
  84         writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr);
  85         writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr);
  86         if (para->bus_width == 32) {
  87                 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr);
  88                 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr);
  89         }
  90         udelay(22);
  91 }
  92
  93 static bool mctl_rank_detect(u32 *gsr0, int rank)
  94 {
  95         const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
  96         const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
  97
  98         mctl_await_completion(gsr0, done, done);
  99         mctl_await_completion(gsr0 + 0x10, done, done);
 100
 101         return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err);
 102 }
 103
 104 static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
 105 {
 106         struct sunxi_mctl_com_reg * const mctl_com =
 107                 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 108         struct sunxi_mctl_ctl_reg *mctl_ctl;
 109         struct sunxi_mctl_phy_reg *mctl_phy;
 110
 111         if (ch_index == 0) {
 112                 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 113                 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
 114         } else {
 115                 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
 116                 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
 117         }
 118
 119         writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd);
 120         mctl_await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
 121
 122         /* PHY initialization */
 123         writel(MCTL_PGCR, &mctl_phy->pgcr);
 124         writel(MCTL_MR0, &mctl_phy->mr0);
 125         writel(MCTL_MR1, &mctl_phy->mr1);
 126         writel(MCTL_MR2, &mctl_phy->mr2);
 127         writel(MCTL_MR3, &mctl_phy->mr3);
 128
 129         writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
 130                &mctl_phy->ptr0);
 131
 132         writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
 133         writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
 134
 135         writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) |
 136                (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) |
 137                (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0),
 138                &mctl_phy->dtpr0);
 139
 140         writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) |
 141                (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) |
 142                ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) |
 143                (MCTL_TAOND << 0), &mctl_phy->dtpr1);
 144
 145         writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) |
 146                (MCTL_TEXSR << 0), &mctl_phy->dtpr2);
 147
 148         writel(1, &mctl_ctl->dfitphyupdtype0);
 149         writel(MCTL_DCR_DDR3, &mctl_phy->dcr);
 150         writel(MCTL_DSGCR, &mctl_phy->dsgcr);
 151         writel(MCTL_DXCCR, &mctl_phy->dxccr);
 152         writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr);
 153         writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr);
 154         writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr);
 155         writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr);
 156
 157         mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03);
 158
 159         writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1);
 160
 161         setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
 162         writel(MCTL_PIR_STEP1, &mctl_phy->pir);
 163         udelay(10);
 164         mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
 165
 166         /* rank detect */
 167         if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) {
 168                 para->rank = 1;
 169                 clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK);
 170         }
 171
 172         /*
 173          * channel detect, check channel 1 dx0 and dx1 have rank 0, if not
 174          * assume nothing is connected to channel 1.
 175          */
 176         if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) {
 177                 para->chan = 1;
 178                 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
 179                 return;
 180         }
 181
 182         /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */
 183         if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) {
 184                 para->bus_width = 16;
 185                 para->page_size = 2048;
 186                 setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE);
 187                 setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE);
 188                 clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN);
 189                 clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN);
 190         }
 191
 192         setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
 193         writel(MCTL_PIR_STEP2, &mctl_phy->pir);
 194         udelay(10);
 195         mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11);
 196
 197         if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK)
 198                 panic("Training error initialising DRAM\n");
 199
 200         /* Move to configure state */
 201         writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl);
 202         mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x01);
 203
 204         /* Set number of clks per micro-second */
 205         writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u);
 206         /* Set number of clks per 100 nano-seconds */
 207         writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n);
 208         /* Set memory timing registers */
 209         writel(MCTL_TREFI, &mctl_ctl->trefi);
 210         writel(MCTL_TMRD, &mctl_ctl->tmrd);
 211         writel(MCTL_TRFC, &mctl_ctl->trfc);
 212         writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp);
 213         writel(MCTL_TRTW, &mctl_ctl->trtw);
 214         writel(MCTL_TAL, &mctl_ctl->tal);
 215         writel(MCTL_TCL, &mctl_ctl->tcl);
 216         writel(MCTL_TCWL, &mctl_ctl->tcwl);
 217         writel(MCTL_TRAS, &mctl_ctl->tras);
 218         writel(MCTL_TRC, &mctl_ctl->trc);
 219         writel(MCTL_TRCD, &mctl_ctl->trcd);
 220         writel(MCTL_TRRD, &mctl_ctl->trrd);
 221         writel(MCTL_TRTP, &mctl_ctl->trtp);
 222         writel(MCTL_TWR, &mctl_ctl->twr);
 223         writel(MCTL_TWTR, &mctl_ctl->twtr);
 224         writel(MCTL_TEXSR, &mctl_ctl->texsr);
 225         writel(MCTL_TXP, &mctl_ctl->txp);
 226         writel(MCTL_TXPDLL, &mctl_ctl->txpdll);
 227         writel(MCTL_TZQCS, &mctl_ctl->tzqcs);
 228         writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi);
 229         writel(MCTL_TDQS, &mctl_ctl->tdqs);
 230         writel(MCTL_TCKSRE, &mctl_ctl->tcksre);
 231         writel(MCTL_TCKSRX, &mctl_ctl->tcksrx);
 232         writel(MCTL_TCKE, &mctl_ctl->tcke);
 233         writel(MCTL_TMOD, &mctl_ctl->tmod);
 234         writel(MCTL_TRSTL, &mctl_ctl->trstl);
 235         writel(MCTL_TZQCL, &mctl_ctl->tzqcl);
 236         writel(MCTL_TMRR, &mctl_ctl->tmrr);
 237         writel(MCTL_TCKESR, &mctl_ctl->tckesr);
 238         writel(MCTL_TDPD, &mctl_ctl->tdpd);
 239
 240         /* Unknown magic performed by boot0 */
 241         setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3);
 242         clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f);
 243
 244         /* Select 16/32-bits mode for MCTL */
 245         if (para->bus_width == 16)
 246                 setbits_le32(&mctl_ctl->ppcfg, 1);
 247
 248         /* Set DFI timing registers */
 249         writel(MCTL_TCWL, &mctl_ctl->dfitphywrl);
 250         writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden);
 251         writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl);
 252         writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0);
 253
 254         writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg);
 255
 256         /* DFI update configuration register */
 257         writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg);
 258
 259         /* Move to access state */
 260         writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl);
 261         mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x03);
 262 }
 263
 264 static void mctl_com_init(struct dram_sun6i_para *para)
 265 {
 266         struct sunxi_mctl_com_reg * const mctl_com =
 267                 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 268         struct sunxi_mctl_phy_reg * const mctl_phy1 =
 269                 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
 270         struct sunxi_prcm_reg * const prcm =
 271                 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 272
 273         writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 |
 274                ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) |
 275                MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
 276                MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr);
 277
 278         /* Unknown magic performed by boot0 */
 279         setbits_le32(&mctl_com->dbgcr, (1 << 6));
 280
 281         if (para->chan == 1) {
 282                 /* Shutdown channel 1 */
 283                 setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE);
 284                 setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE);
 285                 clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE);
 286                 /*
 287                  * CH0 ?? this is what boot0 does. Leave as is until we can
 288                  * confirm this.
 289                  */
 290                 setbits_le32(&prcm->vdd_sys_pwroff,
 291                              PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF);
 292         }
 293 }
 294
 295 static void mctl_port_cfg(void)
 296 {
 297         struct sunxi_mctl_com_reg * const mctl_com =
 298                 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 299         struct sunxi_ccm_reg * const ccm =
 300                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 301
 302         /* enable DRAM AXI clock for CPU access */
 303         setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM);
 304
 305         /* Bunch of magic writes performed by boot0 */
 306         writel(0x00400302, &mctl_com->rmcr[0]);
 307         writel(0x01000307, &mctl_com->rmcr[1]);
 308         writel(0x00400302, &mctl_com->rmcr[2]);
 309         writel(0x01000307, &mctl_com->rmcr[3]);
 310         writel(0x01000307, &mctl_com->rmcr[4]);
 311         writel(0x01000303, &mctl_com->rmcr[6]);
 312         writel(0x01000303, &mctl_com->mmcr[0]);
 313         writel(0x00400310, &mctl_com->mmcr[1]);
 314         writel(0x01000307, &mctl_com->mmcr[2]);
 315         writel(0x01000303, &mctl_com->mmcr[3]);
 316         writel(0x01800303, &mctl_com->mmcr[4]);
 317         writel(0x01800303, &mctl_com->mmcr[5]);
 318         writel(0x01800303, &mctl_com->mmcr[6]);
 319         writel(0x01800303, &mctl_com->mmcr[7]);
 320         writel(0x01000303, &mctl_com->mmcr[8]);
 321         writel(0x00000002, &mctl_com->mmcr[15]);
 322         writel(0x00000310, &mctl_com->mbagcr[0]);
 323         writel(0x00400310, &mctl_com->mbagcr[1]);
 324         writel(0x00400310, &mctl_com->mbagcr[2]);
 325         writel(0x00000307, &mctl_com->mbagcr[3]);
 326         writel(0x00000317, &mctl_com->mbagcr[4]);
 327         writel(0x00000307, &mctl_com->mbagcr[5]);
 328 }
 329
 330 unsigned long sunxi_dram_init(void)
 331 {
 332         struct sunxi_mctl_com_reg * const mctl_com =
 333                 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 334         u32 offset;
 335         int bank, bus, columns;
 336
 337         /* Set initial parameters, these get modified by the autodetect code */
 338         struct dram_sun6i_para para = {
 339                 .bus_width = 32,
 340                 .chan = 2,
 341                 .rank = 2,
 342                 .page_size = 4096,
 343                 .rows = 16,
 344         };
 345
 346         /* A31s only has one channel */
 347         if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S)
 348                 para.chan = 1;
 349
 350         mctl_sys_init();
 351
 352         mctl_dll_init(0, &para);
 353         setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);
 354
 355         if (para.chan == 2) {
 356                 mctl_dll_init(1, &para);
 357                 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
 358         }
 359
 360         setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN);
 361
 362         mctl_channel_init(0, &para);
 363         if (para.chan == 2)
 364                 mctl_channel_init(1, &para);
 365
 366         mctl_com_init(&para);
 367         mctl_port_cfg();
 368
 369         /*
 370          * Change to 1 ch / sequence / 8192 byte pages / 16 rows /
 371          * 8 bit banks / 1 rank mode.
 372          */
 373         clrsetbits_le32(&mctl_com->cr,
 374                 MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK |
 375                     MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
 376                 MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE |
 377                     MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) |
 378                     MCTL_CR_BANK(1) | MCTL_CR_RANK(1));
 379
 380         /* Detect and set page size */
 381         for (columns = 7; columns < 20; columns++) {
 382                 if (mctl_mem_matches(1 << columns))
 383                         break;
 384         }
 385         bus = (para.bus_width == 32) ? 2 : 1;
 386         columns -= bus;
 387         para.page_size = (1 << columns) * (bus << 1);
 388         clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK,
 389                         MCTL_CR_PAGE_SIZE(para.page_size));
 390
 391         /* Detect and set rows */
 392         for (para.rows = 11; para.rows < 16; para.rows++) {
 393                 offset = 1 << (para.rows + columns + bus);
 394                 if (mctl_mem_matches(offset))
 395                         break;
 396         }
 397         clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
 398                         MCTL_CR_ROW(para.rows));
 399
 400         /* Detect bank size */
 401         offset = 1 << (para.rows + columns + bus + 2);
 402         bank = mctl_mem_matches(offset) ? 0 : 1;
 403
 404         /* Restore interleave, chan and rank values, set bank size */
 405         clrsetbits_le32(&mctl_com->cr,
 406                         MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE |
 407                             MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
 408                         MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) |
 409                             MCTL_CR_RANK(para.rank));
 410
 411         return 1 << (para.rank + para.rows + bank + columns + para.chan + bus);
 412 }