arch/arm/mach-socfpga/misc_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <init.h>
   9 #include <asm/io.h>
  10 #include <env.h>
  11 #include <errno.h>
  12 #include <fdtdec.h>
  13 #include <linux/bitops.h>
  14 #include <linux/libfdt.h>
  15 #include <altera.h>
  16 #include <miiphy.h>
  17 #include <netdev.h>
  18 #include <watchdog.h>
  19 #include <asm/arch/misc.h>
  20 #include <asm/arch/reset_manager.h>
  21 #include <asm/arch/scan_manager.h>
  22 #include <asm/arch/sdram.h>
  23 #include <asm/arch/system_manager.h>
  24 #include <asm/arch/nic301.h>
  25 #include <asm/arch/scu.h>
  26 #include <asm/pl310.h>
  27
  28 #include <dt-bindings/reset/altr,rst-mgr.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 static struct pl310_regs *const pl310 =
  33         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  34 static struct nic301_registers *nic301_regs =
  35         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  36 static struct scu_registers *scu_regs =
  37         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  38
  39 /*
  40  * FPGA programming support for SoC FPGA Cyclone V
  41  */
  42 static Altera_desc altera_fpga[] = {
  43         {
  44                 /* Family */
  45                 Altera_SoCFPGA,
  46                 /* Interface type */
  47                 fast_passive_parallel,
  48                 /* No limitation as additional data will be ignored */
  49                 -1,
  50                 /* No device function table */
  51                 NULL,
  52                 /* Base interface address specified in driver */
  53                 NULL,
  54                 /* No cookie implementation */
  55                 0
  56         },
  57 };
  58
  59 static const struct {
  60         const u16       pn;
  61         const char      *name;
  62         const char      *var;
  63 } socfpga_fpga_model[] = {
  64         /* Cyclone V E */
  65         { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
  66         { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
  67         { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
  68         { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
  69         { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
  70         /* Cyclone V GX/GT */
  71         { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
  72         { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
  73         { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
  74         { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
  75         { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
  76         /* Cyclone V SE/SX/ST */
  77         { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
  78         { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
  79         { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
  80         { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
  81         /* Arria V */
  82         { 0x2d03, "Arria V, D5", "av_d5" },
  83         /* Arria V ST/SX */
  84         { 0x2d13, "Arria V, ST/D3 or SX/B3", "av_st_d3" },
  85 };
  86
  87 static int socfpga_fpga_id(const bool print_id)
  88 {
  89         const u32 altera_mi = 0x6e;
  90         const u32 id = scan_mgr_get_fpga_id();
  91
  92         const u32 lsb = id & 0x00000001;
  93         const u32 mi = (id >> 1) & 0x000007ff;
  94         const u32 pn = (id >> 12) & 0x0000ffff;
  95         const u32 version = (id >> 28) & 0x0000000f;
  96         int i;
  97
  98         if ((mi != altera_mi) || (lsb != 1)) {
  99                 printf("FPGA:  Not Altera chip ID\n");
 100                 return -EINVAL;
 101         }
 102
 103         for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
 104                 if (pn == socfpga_fpga_model[i].pn)
 105                         break;
 106
 107         if (i == ARRAY_SIZE(socfpga_fpga_model)) {
 108                 printf("FPGA:  Unknown Altera chip, ID 0x%08x\n", id);
 109                 return -EINVAL;
 110         }
 111
 112         if (print_id)
 113                 printf("FPGA:  Altera %s, version 0x%01x\n",
 114                        socfpga_fpga_model[i].name, version);
 115         return i;
 116 }
 117
 118 /*
 119  * Print CPU information
 120  */
 121 #if defined(CONFIG_DISPLAY_CPUINFO)
 122 int print_cpuinfo(void)
 123 {
 124         const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
 125                                    SYSMGR_GEN5_BOOTINFO);
 126         const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
 127
 128         puts("CPU:   Altera SoCFPGA Platform\n");
 129         socfpga_fpga_id(1);
 130
 131         printf("BOOT:  %s\n", bsel_str[bsel].name);
 132         return 0;
 133 }
 134 #endif
 135
 136 #ifdef CONFIG_ARCH_MISC_INIT
 137 int arch_misc_init(void)
 138 {
 139         const u32 bsel = readl(socfpga_get_sysmgr_addr() +
 140                                SYSMGR_GEN5_BOOTINFO) & 0x7;
 141         const int fpga_id = socfpga_fpga_id(0);
 142         env_set("bootmode", bsel_str[bsel].mode);
 143         if (fpga_id >= 0)
 144                 env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
 145         return 0;
 146 }
 147 #endif
 148
 149 /*
 150  * Convert all NIC-301 AMBA slaves from secure to non-secure
 151  */
 152 static void socfpga_nic301_slave_ns(void)
 153 {
 154         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 155         writel(0x1, &nic301_regs->hps2fpgaregs);
 156         writel(0x1, &nic301_regs->acp);
 157         writel(0x1, &nic301_regs->rom);
 158         writel(0x1, &nic301_regs->ocram);
 159         writel(0x1, &nic301_regs->sdrdata);
 160 }
 161
 162 void socfpga_sdram_remap_zero(void)
 163 {
 164         u32 remap;
 165
 166         socfpga_nic301_slave_ns();
 167
 168         /*
 169          * Private components security:
 170          * U-Boot : configure private timer, global timer and cpu component
 171          * access as non secure for kernel stage (as required by Linux)
 172          */
 173         setbits_le32(&scu_regs->sacr, 0xfff);
 174
 175         /* Configure the L2 controller to make SDRAM start at 0 */
 176         remap = 0x1; /* remap.mpuzero */
 177         /* Keep fpga bridge enabled when running from FPGA onchip RAM */
 178         if (socfpga_is_booting_from_fpga())
 179                 remap |= 0x8; /* remap.hps2fpga */
 180         writel(remap, &nic301_regs->remap);
 181
 182         writel(0x1, &pl310->pl310_addr_filter_start);
 183 }
 184
 185 static u32 iswgrp_handoff[8];
 186
 187 int arch_early_init_r(void)
 188 {
 189         int i;
 190
 191         /*
 192          * Write magic value into magic register to unlock support for
 193          * issuing warm reset. The ancient kernel code expects this
 194          * value to be written into the register by the bootloader, so
 195          * to support that old code, we write it here instead of in the
 196          * reset_cpu() function just before resetting the CPU.
 197          */
 198         writel(0xae9efebc,
 199                socfpga_get_sysmgr_addr() + SYSMGR_GEN5_WARMRAMGRP_EN);
 200
 201         for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
 202                 iswgrp_handoff[i] = readl(socfpga_get_sysmgr_addr() +
 203                                           SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
 204
 205         socfpga_bridges_reset(1);
 206
 207         socfpga_sdram_remap_zero();
 208
 209         /* Add device descriptor to FPGA device table */
 210         socfpga_fpga_add(&altera_fpga[0]);
 211
 212         return 0;
 213 }
 214
 215 #ifndef CONFIG_SPL_BUILD
 216 static struct socfpga_sdr_ctrl *sdr_ctrl =
 217         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 218
 219 void do_bridge_reset(int enable, unsigned int mask)
 220 {
 221         int i;
 222
 223         if (enable) {
 224                 socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
 225                                                  !(mask & BIT(1)),
 226                                                  !(mask & BIT(2)));
 227                 for (i = 0; i < 2; i++) {       /* Reload SW setting cache */
 228                         iswgrp_handoff[i] =
 229                                 readl(socfpga_get_sysmgr_addr() +
 230                                       SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
 231                 }
 232
 233                 writel(iswgrp_handoff[2],
 234                        socfpga_get_sysmgr_addr() +
 235                        SYSMGR_GEN5_FPGAINFGRP_MODULE);
 236                 writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
 237                 writel(iswgrp_handoff[0],
 238                        socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 239                 writel(iswgrp_handoff[1], &nic301_regs->remap);
 240
 241                 writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 242                 writel(iswgrp_handoff[0],
 243                        socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 244         } else {
 245                 writel(0, socfpga_get_sysmgr_addr() +
 246                        SYSMGR_GEN5_FPGAINFGRP_MODULE);
 247                 writel(0, &sdr_ctrl->fpgaport_rst);
 248                 writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 249                 writel(1, &nic301_regs->remap);
 250         }
 251 }
 252 #endif