arch/arm/mach-socfpga/misc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <cpu_func.h>
   9 #include <hang.h>
  10 #include <asm/cache.h>
  11 #include <init.h>
  12 #include <asm/io.h>
  13 #include <errno.h>
  14 #include <fdtdec.h>
  15 #include <linux/libfdt.h>
  16 #include <altera.h>
  17 #include <miiphy.h>
  18 #include <netdev.h>
  19 #include <watchdog.h>
  20 #include <asm/arch/misc.h>
  21 #include <asm/arch/reset_manager.h>
  22 #include <asm/arch/scan_manager.h>
  23 #include <asm/arch/system_manager.h>
  24 #include <asm/arch/nic301.h>
  25 #include <asm/arch/scu.h>
  26 #include <asm/pl310.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 phys_addr_t socfpga_clkmgr_base __section(".data");
  31 phys_addr_t socfpga_rstmgr_base __section(".data");
  32 phys_addr_t socfpga_sysmgr_base __section(".data");
  33
  34 #ifdef CONFIG_SYS_L2_PL310
  35 static const struct pl310_regs *const pl310 =
  36         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  37 #endif
  38
  39 struct bsel bsel_str[] = {
  40         { "rsvd", "Reserved", },
  41         { "fpga", "FPGA (HPS2FPGA Bridge)", },
  42         { "nand", "NAND Flash (1.8V)", },
  43         { "nand", "NAND Flash (3.0V)", },
  44         { "sd", "SD/MMC External Transceiver (1.8V)", },
  45         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  46         { "qspi", "QSPI Flash (1.8V)", },
  47         { "qspi", "QSPI Flash (3.0V)", },
  48 };
  49
  50 int dram_init(void)
  51 {
  52         if (fdtdec_setup_mem_size_base() != 0)
  53                 return -EINVAL;
  54
  55         return 0;
  56 }
  57
  58 void enable_caches(void)
  59 {
  60 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  61         icache_enable();
  62 #endif
  63 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  64         dcache_enable();
  65 #endif
  66 }
  67
  68 #ifdef CONFIG_SYS_L2_PL310
  69 void v7_outer_cache_enable(void)
  70 {
  71         struct udevice *dev;
  72
  73         if (uclass_get_device(UCLASS_CACHE, 0, &dev))
  74                 pr_err("cache controller driver NOT found!\n");
  75 }
  76
  77 void v7_outer_cache_disable(void)
  78 {
  79         /* Disable the L2 cache */
  80         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  81 }
  82
  83 void socfpga_pl310_clear(void)
  84 {
  85         u32 mask = 0xff, ena = 0;
  86
  87         icache_enable();
  88
  89         /* Disable the L2 cache */
  90         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  91
  92         writel(0x0, &pl310->pl310_tag_latency_ctrl);
  93         writel(0x10, &pl310->pl310_data_latency_ctrl);
  94
  95         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  96         setbits_le32(&pl310->pl310_aux_ctrl,
  97                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  98                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  99                      L310_SHARED_ATT_OVERRIDE_ENABLE);
 100
 101         /* Enable the L2 cache */
 102         ena = readl(&pl310->pl310_ctrl);
 103         ena |= L2X0_CTRL_EN;
 104
 105         /*
 106          * Invalidate the PL310 L2 cache. Keep the invalidation code
 107          * entirely in L1 I-cache to avoid any bus traffic through
 108          * the L2.
 109          */
 110         asm volatile(
 111                 ".align 5                       \n"
 112                 "       b       3f              \n"
 113                 "1:     str     %1,     [%4]    \n"
 114                 "       dsb                     \n"
 115                 "       isb                     \n"
 116                 "       str     %0,     [%2]    \n"
 117                 "       dsb                     \n"
 118                 "       isb                     \n"
 119                 "2:     ldr     %0,     [%2]    \n"
 120                 "       cmp     %0,     #0      \n"
 121                 "       bne     2b              \n"
 122                 "       str     %0,     [%3]    \n"
 123                 "       dsb                     \n"
 124                 "       isb                     \n"
 125                 "       b       4f              \n"
 126                 "3:     b       1b              \n"
 127                 "4:     nop                     \n"
 128         : "+r"(mask), "+r"(ena)
 129         : "r"(&pl310->pl310_inv_way),
 130           "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
 131         : "memory", "cc");
 132
 133         /* Disable the L2 cache */
 134         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 135 }
 136 #endif
 137
 138 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 139 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 140 int overwrite_console(void)
 141 {
 142         return 0;
 143 }
 144 #endif
 145
 146 #ifdef CONFIG_FPGA
 147 /* add device descriptor to FPGA device table */
 148 void socfpga_fpga_add(void *fpga_desc)
 149 {
 150         fpga_init();
 151         fpga_add(fpga_altera, fpga_desc);
 152 }
 153 #endif
 154
 155 int arch_cpu_init(void)
 156 {
 157         socfpga_get_managers_addr();
 158
 159 #ifdef CONFIG_HW_WATCHDOG
 160         /*
 161          * In case the watchdog is enabled, make sure to (re-)configure it
 162          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 163          * timeout value is still active which might too short for Linux
 164          * booting.
 165          */
 166         hw_watchdog_init();
 167 #else
 168         /*
 169          * If the HW watchdog is NOT enabled, make sure it is not running,
 170          * for example because it was enabled in the preloader. This might
 171          * trigger a watchdog-triggered reboot of Linux kernel later.
 172          * Toggle watchdog reset, so watchdog in not running state.
 173          */
 174         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 175         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 176 #endif
 177
 178         return 0;
 179 }
 180
 181 #ifndef CONFIG_SPL_BUILD
 182 static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc,
 183                      char *const argv[])
 184 {
 185         unsigned int mask = ~0;
 186
 187         if (argc < 2 || argc > 3)
 188                 return CMD_RET_USAGE;
 189
 190         argv++;
 191
 192         if (argc == 3)
 193                 mask = simple_strtoul(argv[1], NULL, 16);
 194
 195         switch (*argv[0]) {
 196         case 'e':       /* Enable */
 197                 do_bridge_reset(1, mask);
 198                 break;
 199         case 'd':       /* Disable */
 200                 do_bridge_reset(0, mask);
 201                 break;
 202         default:
 203                 return CMD_RET_USAGE;
 204         }
 205
 206         return 0;
 207 }
 208
 209 U_BOOT_CMD(bridge, 3, 1, do_bridge,
 210            "SoCFPGA HPS FPGA bridge control",
 211            "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 212            "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 213            ""
 214 );
 215
 216 #endif
 217
 218 static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
 219 {
 220         const void *blob = gd->fdt_blob;
 221         struct fdt_resource r;
 222         int node;
 223         int ret;
 224
 225         node = fdt_node_offset_by_compatible(blob, -1, compat);
 226         if (node < 0)
 227                 return node;
 228
 229         if (!fdtdec_get_is_enabled(blob, node))
 230                 return -ENODEV;
 231
 232         ret = fdt_get_resource(blob, node, "reg", 0, &r);
 233         if (ret)
 234                 return ret;
 235
 236         *base = (phys_addr_t)r.start;
 237
 238         return 0;
 239 }
 240
 241 void socfpga_get_managers_addr(void)
 242 {
 243         int ret;
 244
 245         ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
 246         if (ret)
 247                 hang();
 248
 249         ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
 250         if (ret)
 251                 hang();
 252
 253 #ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 254         ret = socfpga_get_base_addr("intel,agilex-clkmgr",
 255                                     &socfpga_clkmgr_base);
 256 #else
 257         ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
 258 #endif
 259         if (ret)
 260                 hang();
 261 }
 262
 263 phys_addr_t socfpga_get_rstmgr_addr(void)
 264 {
 265         return socfpga_rstmgr_base;
 266 }
 267
 268 phys_addr_t socfpga_get_sysmgr_addr(void)
 269 {
 270         return socfpga_sysmgr_base;
 271 }
 272
 273 phys_addr_t socfpga_get_clkmgr_addr(void)
 274 {
 275         return socfpga_clkmgr_base;
 276 }