1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
6 #ifndef _SYSTEM_MANAGER_H_
7 #define _SYSTEM_MANAGER_H_
9 phys_addr_t socfpga_get_sysmgr_addr(void);
11 #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
12 defined(CONFIG_TARGET_SOCFPGA_AGILEX)
13 #include <asm/arch/system_manager_soc64.h>
15 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
16 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
17 #define SYSMGR_ECC_OCRAM_EN BIT(0)
18 #define SYSMGR_ECC_OCRAM_SERR BIT(3)
19 #define SYSMGR_ECC_OCRAM_DERR BIT(4)
20 #define SYSMGR_FPGAINTF_USEFPGA 0x1
21 #define SYSMGR_FPGAINTF_SPIM0 BIT(0)
22 #define SYSMGR_FPGAINTF_SPIM1 BIT(1)
23 #define SYSMGR_FPGAINTF_EMAC0 BIT(2)
24 #define SYSMGR_FPGAINTF_EMAC1 BIT(3)
25 #define SYSMGR_FPGAINTF_NAND BIT(4)
26 #define SYSMGR_FPGAINTF_SDMMC BIT(5)
28 #define SYSMGR_SDMMC_DRVSEL_SHIFT 0
30 /* EMAC Group Bit definitions */
31 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
32 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
33 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
35 #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
36 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
37 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
39 /* For dedicated IO configuration */
40 /* Voltage select enums */
41 #define VOLTAGE_SEL_3V 0x0
42 #define VOLTAGE_SEL_1P8V 0x1
43 #define VOLTAGE_SEL_2P5V 0x2
45 /* Input buffer enable */
46 #define INPUT_BUF_DISABLE 0
47 #define INPUT_BUF_1P8V 1
48 #define INPUT_BUF_2P5V3V 2
50 /* Weak pull up enable */
51 #define WK_PU_DISABLE 0
52 #define WK_PU_ENABLE 1
54 /* Pull up slew rate control */
55 #define PU_SLW_RT_SLOW 0
56 #define PU_SLW_RT_FAST 1
57 #define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW
59 /* Pull down slew rate control */
60 #define PD_SLW_RT_SLOW 0
61 #define PD_SLW_RT_FAST 1
62 #define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW
64 /* Drive strength control */
65 #define PU_DRV_STRG_DEFAULT 0x10
66 #define PD_DRV_STRG_DEFAULT 0x10
69 #define PD_DRV_STRG_LSB 0
70 #define PD_SLW_RT_LSB 5
71 #define PU_DRV_STRG_LSB 8
72 #define PU_SLW_RT_LSB 13
74 #define INPUT_BUF_LSB 17
75 #define BIAS_TRIM_LSB 19
76 #define VOLTAGE_SEL_LSB 0
78 #define ALT_SYSMGR_NOC_H2F_SET_MSK BIT(0)
79 #define ALT_SYSMGR_NOC_LWH2F_SET_MSK BIT(4)
80 #define ALT_SYSMGR_NOC_F2H_SET_MSK BIT(8)
81 #define ALT_SYSMGR_NOC_F2SDR0_SET_MSK BIT(16)
82 #define ALT_SYSMGR_NOC_F2SDR1_SET_MSK BIT(20)
83 #define ALT_SYSMGR_NOC_F2SDR2_SET_MSK BIT(24)
84 #define ALT_SYSMGR_NOC_TMO_EN_SET_MSK BIT(0)
86 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK BIT(1)
87 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK BIT(1)
89 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
90 #include <asm/arch/system_manager_gen5.h>
91 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
92 #include <asm/arch/system_manager_arria10.h>
95 #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
96 (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
97 #include <linux/bitops.h>
99 #endif /* _SYSTEM_MANAGER_H_ */