1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
10 #include <linux/bitops.h>
12 struct socfpga_firwall_l4_per {
44 struct socfpga_firwall_l4_sys {
45 u32 _pad_0x00; /* 0x00 */
49 u32 emac0tx_ecc; /* 0x10 */
53 u32 emac2tx_ecc; /* 0x20 */
57 u32 nand_read_ecc; /* 0x30 */
61 u32 sdmmc_ecc; /* 0x40 */
65 u32 _pad_0x50; /* 0x50 */
69 u32 osc0_timer; /* 0x60 */
73 u32 watchdog2; /* 0x70 */
77 #define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16))
78 #define FIREWALL_BRIDGE_DISABLE_ALL (~0)
80 /* Cache coherency unit (CCU) registers */
81 #define CCU_CPU0_MPRT_ADBASE_DDRREG 0x4400
82 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE0 0x45c0
83 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A 0x45e0
84 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B 0x4600
85 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C 0x4620
86 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D 0x4640
87 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E 0x4660
89 #define CCU_CPU0_MPRT_ADMASK_MEM_RAM0 0x4688
91 #define CCU_IOM_MPRT_ADBASE_MEMSPACE0 0x18560
92 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1A 0x18580
93 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1B 0x185a0
94 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1C 0x185c0
95 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1D 0x185e0
96 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1E 0x18600
98 #define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628
100 #define CCU_TCU_MPRT_ADBASE_MEMSPACE0 0x2c520
101 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1A 0x2c540
102 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1B 0x2c560
103 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1C 0x2c580
104 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1D 0x2c5a0
105 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1E 0x2c5c0
107 #define CCU_ADMASK_P_MASK BIT(0)
108 #define CCU_ADMASK_NS_MASK BIT(1)
110 #define CCU_ADBASE_DI_MASK BIT(4)
112 #define CCU_REG_ADDR(reg) \
113 (SOCFPGA_CCU_ADDRESS + (reg))
115 /* Firewall MPU DDR SCR registers */
116 #define FW_MPU_DDR_SCR_EN 0x00
117 #define FW_MPU_DDR_SCR_EN_SET 0x04
118 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT 0x18
119 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
120 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
121 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
123 #define MPUREGION0_ENABLE BIT(0)
124 #define NONMPUREGION0_ENABLE BIT(8)
126 #define FW_MPU_DDR_SCR_WRITEL(data, reg) \
127 writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
129 void firewall_setup(void);
131 #endif /* _FIREWALL_H_ */