arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #ifndef _CLOCK_MANAGER_GEN5_H_
   7 #define _CLOCK_MANAGER_GEN5_H_
   8
   9 #ifndef __ASSEMBLY__
  10
  11 #include <linux/bitops.h>
  12
  13 struct cm_config {
  14         /* main group */
  15         u32 main_vco_base;
  16         u32 mpuclk;
  17         u32 mainclk;
  18         u32 dbgatclk;
  19         u32 mainqspiclk;
  20         u32 mainnandsdmmcclk;
  21         u32 cfg2fuser0clk;
  22         u32 maindiv;
  23         u32 dbgdiv;
  24         u32 tracediv;
  25         u32 l4src;
  26
  27         /* peripheral group */
  28         u32 peri_vco_base;
  29         u32 emac0clk;
  30         u32 emac1clk;
  31         u32 perqspiclk;
  32         u32 pernandsdmmcclk;
  33         u32 perbaseclk;
  34         u32 s2fuser1clk;
  35         u32 perdiv;
  36         u32 gpiodiv;
  37         u32 persrc;
  38
  39         /* sdram pll group */
  40         u32 sdram_vco_base;
  41         u32 ddrdqsclk;
  42         u32 ddr2xdqsclk;
  43         u32 ddrdqclk;
  44         u32 s2fuser2clk;
  45
  46         /* altera group */
  47         u32 altera_grp_mpuclk;
  48 };
  49
  50 /* Clock manager group */
  51 #define CLKMGR_GEN5_CTRL                        0x00
  52 #define CLKMGR_GEN5_BYPASS                      0x04
  53 #define CLKMGR_GEN5_INTER                       0x08
  54 #define CLKMGR_GEN5_STAT                        0x14
  55 /* MainPLL group */
  56 #define CLKMGR_GEN5_MAINPLL_VCO                 0x40
  57 #define CLKMGR_GEN5_MAINPLL_MISC                0x44
  58 #define CLKMGR_GEN5_MAINPLL_MPUCLK              0x48
  59 #define CLKMGR_GEN5_MAINPLL_MAINCLK             0x4c
  60 #define CLKMGR_GEN5_MAINPLL_DBGATCLK            0x50
  61 #define CLKMGR_GEN5_MAINPLL_MAINQSPICLK         0x54
  62 #define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK    0x58
  63 #define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK      0x5c
  64 #define CLKMGR_GEN5_MAINPLL_EN                  0x60
  65 #define CLKMGR_GEN5_MAINPLL_MAINDIV             0x64
  66 #define CLKMGR_GEN5_MAINPLL_DBGDIV              0x68
  67 #define CLKMGR_GEN5_MAINPLL_TRACEDIV            0x6c
  68 #define CLKMGR_GEN5_MAINPLL_L4SRC               0x70
  69 /* Peripheral PLL group */
  70 #define CLKMGR_GEN5_PERPLL_VCO                  0x80
  71 #define CLKMGR_GEN5_PERPLL_MISC                 0x84
  72 #define CLKMGR_GEN5_PERPLL_EMAC0CLK             0x88
  73 #define CLKMGR_GEN5_PERPLL_EMAC1CLK             0x8c
  74 #define CLKMGR_GEN5_PERPLL_PERQSPICLK           0x90
  75 #define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK      0x94
  76 #define CLKMGR_GEN5_PERPLL_PERBASECLK           0x98
  77 #define CLKMGR_GEN5_PERPLL_S2FUSER1CLK          0x9c
  78 #define CLKMGR_GEN5_PERPLL_EN                   0xa0
  79 #define CLKMGR_GEN5_PERPLL_DIV                  0xa4
  80 #define CLKMGR_GEN5_PERPLL_GPIODIV              0xa8
  81 #define CLKMGR_GEN5_PERPLL_SRC                  0xac
  82 /* SDRAM PLL group */
  83 #define CLKMGR_GEN5_SDRPLL_VCO                  0xc0
  84 #define CLKMGR_GEN5_SDRPLL_CTRL                 0xc4
  85 #define CLKMGR_GEN5_SDRPLL_DDRDQSCLK            0xc8
  86 #define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK          0xcc
  87 #define CLKMGR_GEN5_SDRPLL_DDRDQCLK             0xd0
  88 #define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK          0xd4
  89 #define CLKMGR_GEN5_SDRPLL_EN                   0xd8
  90 /* Altera group */
  91 #define CLKMGR_GEN5_ALTR_MPUCLK                 0xe0
  92 #define CLKMGR_GEN5_ALTR_MAINCLK                0xe4
  93
  94 #define CLKMGR_STAT                             CLKMGR_GEN5_STAT
  95 #define CLKMGR_INTER                            CLKMGR_GEN5_INTER
  96 #define CLKMGR_PERPLL_EN                        CLKMGR_GEN5_PERPLL_EN
  97
  98 /* Clock speed accessors */
  99 unsigned long cm_get_mpu_clk_hz(void);
 100 unsigned long cm_get_sdram_clk_hz(void);
 101 unsigned int cm_get_l4_sp_clk_hz(void);
 102 unsigned int cm_get_mmc_controller_clk_hz(void);
 103 unsigned int cm_get_qspi_controller_clk_hz(void);
 104 unsigned int cm_get_spi_controller_clk_hz(void);
 105 const unsigned int cm_get_osc_clk_hz(const int osc);
 106 const unsigned int cm_get_f2s_per_ref_clk_hz(void);
 107 const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
 108
 109 /* Clock configuration accessors */
 110 int cm_basic_init(const struct cm_config * const cfg);
 111 const struct cm_config * const cm_get_default_config(void);
 112 #endif /* __ASSEMBLY__ */
 113
 114 #include <linux/bitops.h>
 115 #define LOCKED_MASK \
 116         (CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
 117         CLKMGR_INTER_PERPLLLOCKED_MASK  | \
 118         CLKMGR_INTER_MAINPLLLOCKED_MASK)
 119
 120 #define CLKMGR_CTRL_SAFEMODE                            BIT(0)
 121 #define CLKMGR_CTRL_SAFEMODE_OFFSET                     0
 122
 123 #define CLKMGR_BYPASS_PERPLLSRC                         BIT(4)
 124 #define CLKMGR_BYPASS_PERPLLSRC_OFFSET                  4
 125 #define CLKMGR_BYPASS_PERPLL                            BIT(3)
 126 #define CLKMGR_BYPASS_PERPLL_OFFSET                     3
 127 #define CLKMGR_BYPASS_SDRPLLSRC                         BIT(2)
 128 #define CLKMGR_BYPASS_SDRPLLSRC_OFFSET                  2
 129 #define CLKMGR_BYPASS_SDRPLL                            BIT(1)
 130 #define CLKMGR_BYPASS_SDRPLL_OFFSET                     1
 131 #define CLKMGR_BYPASS_MAINPLL                           BIT(0)
 132 #define CLKMGR_BYPASS_MAINPLL_OFFSET                    0
 133
 134 #define CLKMGR_INTER_MAINPLLLOST_MASK                   BIT(3)
 135 #define CLKMGR_INTER_PERPLLLOST_MASK                    BIT(4)
 136 #define CLKMGR_INTER_SDRPLLLOST_MASK                    BIT(5)
 137 #define CLKMGR_INTER_MAINPLLLOCKED_MASK                 BIT(6)
 138 #define CLKMGR_INTER_PERPLLLOCKED_MASK                  BIT(7)
 139 #define CLKMGR_INTER_SDRPLLLOCKED_MASK                  BIT(8)
 140
 141 #define CLKMGR_STAT_BUSY                                BIT(0)
 142
 143 /* Main PLL */
 144 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN                   BIT(0)
 145 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET            0
 146 #define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET              16
 147 #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK                0x003f0000
 148 #define CLKMGR_MAINPLLGRP_VCO_EN                        BIT(1)
 149 #define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET                 1
 150 #define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET              3
 151 #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK                0x0000fff8
 152 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK          0x01000000
 153 #define CLKMGR_MAINPLLGRP_VCO_PWRDN                     BIT(2)
 154 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET              2
 155 #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK            0x80000000
 156 #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE               0x8001000d
 157
 158 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET             0
 159 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK               0x000001ff
 160
 161 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET            0
 162 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK              0x000001ff
 163
 164 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET           0
 165 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK             0x000001ff
 166
 167 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET        0
 168 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK          0x000001ff
 169
 170 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET   0
 171 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK     0x000001ff
 172
 173 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET     0
 174 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK       0x000001ff
 175
 176 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK               BIT(2)
 177 #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK              BIT(4)
 178 #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK                BIT(5)
 179 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK           BIT(6)
 180 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK           BIT(7)
 181 #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK           BIT(9)
 182
 183 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET        0
 184 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK          0x00000003
 185 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET        2
 186 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK          0x0000000c
 187 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET        4
 188 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK          0x00000070
 189 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET        7
 190 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK          0x00000380
 191
 192 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET        0
 193 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK          0x00000003
 194 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET          2
 195 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK            0x0000000c
 196
 197 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET      0
 198 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK        0x00000007
 199
 200 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP                    BIT(0)
 201 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET             0
 202 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP                    BIT(1)
 203 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET             1
 204 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE             0x00000000
 205 #define CLKMGR_L4_SP_CLK_SRC_MAINPLL                    0x0
 206 #define CLKMGR_L4_SP_CLK_SRC_PERPLL                     0x1
 207
 208 /* Per PLL */
 209 #define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET               16
 210 #define CLKMGR_PERPLLGRP_VCO_DENOM_MASK                 0x003f0000
 211 #define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET               3
 212 #define CLKMGR_PERPLLGRP_VCO_NUMER_MASK                 0x0000fff8
 213 #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK           0x01000000
 214 #define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET                22
 215 #define CLKMGR_PERPLLGRP_VCO_PSRC_MASK                  0x00c00000
 216 #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK             0x80000000
 217 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE                0x8001000d
 218 #define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET                22
 219 #define CLKMGR_PERPLLGRP_VCO_SSRC_MASK                  0x00c00000
 220
 221 #define CLKMGR_VCO_SSRC_EOSC1                           0x0
 222 #define CLKMGR_VCO_SSRC_EOSC2                           0x1
 223 #define CLKMGR_VCO_SSRC_F2S                             0x2
 224
 225 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET            0
 226 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK              0x000001ff
 227
 228 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET            0
 229 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK              0x000001ff
 230
 231 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET          0
 232 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK            0x000001ff
 233
 234 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET     0
 235 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK       0x000001ff
 236
 237 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET          0
 238 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK            0x000001ff
 239
 240 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET         0
 241 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK           0x000001ff
 242
 243 #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK                0x00000400
 244 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK               0x00000100
 245
 246 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET             6
 247 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK               0x000001c0
 248 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET             9
 249 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK               0x00000e00
 250 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET             3
 251 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET             3
 252 #define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET              0
 253 #define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK                0x00000007
 254
 255 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET       0
 256 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK         0x00ffffff
 257
 258 #define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET                2
 259 #define CLKMGR_PERPLLGRP_SRC_NAND_MASK                  0x0000000c
 260 #define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET                4
 261 #define CLKMGR_PERPLLGRP_SRC_QSPI_MASK                  0x00000030
 262 #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE                0x00000015
 263 #define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET               0
 264 #define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK                 0x00000003
 265 #define CLKMGR_SDMMC_CLK_SRC_F2S                        0x0
 266 #define CLKMGR_SDMMC_CLK_SRC_MAIN                       0x1
 267 #define CLKMGR_SDMMC_CLK_SRC_PER                        0x2
 268 #define CLKMGR_QSPI_CLK_SRC_F2S                         0x0
 269 #define CLKMGR_QSPI_CLK_SRC_MAIN                        0x1
 270 #define CLKMGR_QSPI_CLK_SRC_PER                         0x2
 271
 272 /* SDR PLL */
 273 #define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET               16
 274 #define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK                 0x003f0000
 275 #define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET               3
 276 #define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK                 0x0000fff8
 277 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL                BIT(24)
 278 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET         24
 279 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET            25
 280 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK              0x7e000000
 281 #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK             BIT(31)
 282 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE                0x8001000d
 283 #define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET                22
 284 #define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK                  0x00c00000
 285
 286 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET           0
 287 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK             0x000001ff
 288 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET         9
 289 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK           0x00000e00
 290
 291 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET         0
 292 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK           0x000001ff
 293 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET       9
 294 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK         0x00000e00
 295
 296 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET            0
 297 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK              0x000001ff
 298 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET          9
 299 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK            0x00000e00
 300
 301 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET         0
 302 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK           0x000001ff
 303 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET       9
 304 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK         0x00000e00
 305
 306 #endif /* _CLOCK_MANAGER_GEN5_H_ */