arch/arm/mach-socfpga/clock_manager_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2017 Intel Corporation
   4  */
   5
   6 #include <common.h>
   7 #include <fdtdec.h>
   8 #include <malloc.h>
   9 #include <asm/io.h>
  10 #include <dm.h>
  11 #include <clk.h>
  12 #include <dm/device-internal.h>
  13 #include <asm/arch/clock_manager.h>
  14 #include <linux/delay.h>
  15
  16 #ifdef CONFIG_SPL_BUILD
  17
  18 static u32 eosc1_hz;
  19 static u32 cb_intosc_hz;
  20 static u32 f2s_free_hz;
  21
  22 struct mainpll_cfg {
  23         u32 vco0_psrc;
  24         u32 vco1_denom;
  25         u32 vco1_numer;
  26         u32 mpuclk;
  27         u32 mpuclk_cnt;
  28         u32 mpuclk_src;
  29         u32 nocclk;
  30         u32 nocclk_cnt;
  31         u32 nocclk_src;
  32         u32 cntr2clk_cnt;
  33         u32 cntr3clk_cnt;
  34         u32 cntr4clk_cnt;
  35         u32 cntr5clk_cnt;
  36         u32 cntr6clk_cnt;
  37         u32 cntr7clk_cnt;
  38         u32 cntr7clk_src;
  39         u32 cntr8clk_cnt;
  40         u32 cntr9clk_cnt;
  41         u32 cntr9clk_src;
  42         u32 cntr15clk_cnt;
  43         u32 nocdiv_l4mainclk;
  44         u32 nocdiv_l4mpclk;
  45         u32 nocdiv_l4spclk;
  46         u32 nocdiv_csatclk;
  47         u32 nocdiv_cstraceclk;
  48         u32 nocdiv_cspdbclk;
  49 };
  50
  51 struct perpll_cfg {
  52         u32 vco0_psrc;
  53         u32 vco1_denom;
  54         u32 vco1_numer;
  55         u32 cntr2clk_cnt;
  56         u32 cntr2clk_src;
  57         u32 cntr3clk_cnt;
  58         u32 cntr3clk_src;
  59         u32 cntr4clk_cnt;
  60         u32 cntr4clk_src;
  61         u32 cntr5clk_cnt;
  62         u32 cntr5clk_src;
  63         u32 cntr6clk_cnt;
  64         u32 cntr6clk_src;
  65         u32 cntr7clk_cnt;
  66         u32 cntr8clk_cnt;
  67         u32 cntr8clk_src;
  68         u32 cntr9clk_cnt;
  69         u32 cntr9clk_src;
  70         u32 emacctl_emac0sel;
  71         u32 emacctl_emac1sel;
  72         u32 emacctl_emac2sel;
  73         u32 gpiodiv_gpiodbclk;
  74 };
  75
  76 struct strtou32 {
  77         const char *str;
  78         const u32 val;
  79 };
  80
  81 static const struct strtou32 mainpll_cfg_tab[] = {
  82         { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) },
  83         { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) },
  84         { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) },
  85         { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) },
  86         { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) },
  87         { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) },
  88         { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) },
  89         { "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt) },
  90         { "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt) },
  91         { "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt) },
  92         { "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt) },
  93         { "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt) },
  94         { "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt) },
  95         { "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src) },
  96         { "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt) },
  97         { "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt) },
  98         { "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src) },
  99         { "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) },
 100         { "nocdiv-l4mainclk", offsetof(struct mainpll_cfg, nocdiv_l4mainclk) },
 101         { "nocdiv-l4mpclk", offsetof(struct mainpll_cfg, nocdiv_l4mpclk) },
 102         { "nocdiv-l4spclk", offsetof(struct mainpll_cfg, nocdiv_l4spclk) },
 103         { "nocdiv-csatclk", offsetof(struct mainpll_cfg, nocdiv_csatclk) },
 104         { "nocdiv-cstraceclk", offsetof(struct mainpll_cfg, nocdiv_cstraceclk) },
 105         { "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg, nocdiv_cspdbclk) },
 106 };
 107
 108 static const struct strtou32 perpll_cfg_tab[] = {
 109         { "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) },
 110         { "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) },
 111         { "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) },
 112         { "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt) },
 113         { "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src) },
 114         { "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt) },
 115         { "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src) },
 116         { "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt) },
 117         { "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src) },
 118         { "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt) },
 119         { "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src) },
 120         { "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt) },
 121         { "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src) },
 122         { "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt) },
 123         { "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt) },
 124         { "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src) },
 125         { "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt) },
 126         { "emacctl-emac0sel", offsetof(struct perpll_cfg, emacctl_emac0sel) },
 127         { "emacctl-emac1sel", offsetof(struct perpll_cfg, emacctl_emac1sel) },
 128         { "emacctl-emac2sel", offsetof(struct perpll_cfg, emacctl_emac2sel) },
 129         { "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg, gpiodiv_gpiodbclk) },
 130 };
 131
 132 static const struct strtou32 alteragrp_cfg_tab[] = {
 133         { "nocclk", offsetof(struct mainpll_cfg, nocclk) },
 134         { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) },
 135 };
 136
 137 struct strtopu32 {
 138         const char *str;
 139         u32 *p;
 140 };
 141
 142 const struct strtopu32 dt_to_val[] = {
 143         { "altera_arria10_hps_eosc1", &eosc1_hz },
 144         { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz },
 145         { "altera_arria10_hps_f2h_free", &f2s_free_hz },
 146 };
 147
 148 static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab,
 149                         int cfg_tab_len, void *cfg)
 150 {
 151         int i;
 152         u32 val;
 153
 154         for (i = 0; i < cfg_tab_len; i++) {
 155                 if (fdtdec_get_int_array(blob, node, cfg_tab[i].str, &val, 1)) {
 156                         /* could not find required property */
 157                         return -EINVAL;
 158                 }
 159                 *(u32 *)(cfg + cfg_tab[i].val) = val;
 160         }
 161
 162         return 0;
 163 }
 164
 165 static int of_get_input_clks(const void *blob)
 166 {
 167         struct udevice *dev;
 168         struct clk clk;
 169         int i, ret;
 170
 171         for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
 172                 memset(&clk, 0, sizeof(clk));
 173
 174                 ret = uclass_get_device_by_name(UCLASS_CLK, dt_to_val[i].str,
 175                                                 &dev);
 176                 if (ret)
 177                         return ret;
 178
 179                 ret = clk_request(dev, &clk);
 180                 if (ret)
 181                         return ret;
 182
 183                 *dt_to_val[i].p = clk_get_rate(&clk);
 184         }
 185
 186         return 0;
 187 }
 188
 189 static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
 190                           struct perpll_cfg *per_cfg)
 191 {
 192         int ret, node, child, len;
 193         const char *node_name;
 194
 195         ret = of_get_input_clks(blob);
 196         if (ret)
 197                 return ret;
 198
 199         node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT);
 200
 201         if (node < 0)
 202                 return -EINVAL;
 203
 204         child = fdt_first_subnode(blob, node);
 205
 206         if (child < 0)
 207                 return -EINVAL;
 208
 209         node_name = fdt_get_name(blob, child, &len);
 210
 211         while (node_name) {
 212                 if (!strcmp(node_name, "mainpll")) {
 213                         if (of_to_struct(blob, child, mainpll_cfg_tab,
 214                                          ARRAY_SIZE(mainpll_cfg_tab), main_cfg))
 215                                 return -EINVAL;
 216                 } else if (!strcmp(node_name, "perpll")) {
 217                         if (of_to_struct(blob, child, perpll_cfg_tab,
 218                                          ARRAY_SIZE(perpll_cfg_tab), per_cfg))
 219                                 return -EINVAL;
 220                 } else if (!strcmp(node_name, "alteragrp")) {
 221                         if (of_to_struct(blob, child, alteragrp_cfg_tab,
 222                                          ARRAY_SIZE(alteragrp_cfg_tab), main_cfg))
 223                                 return -EINVAL;
 224                 }
 225                 child = fdt_next_subnode(blob, child);
 226
 227                 if (child < 0)
 228                         break;
 229
 230                 node_name = fdt_get_name(blob, child, &len);
 231         }
 232
 233         return 0;
 234 }
 235
 236 /* calculate the intended main VCO frequency based on handoff */
 237 static unsigned int cm_calc_handoff_main_vco_clk_hz
 238                                         (struct mainpll_cfg *main_cfg)
 239 {
 240         unsigned int clk_hz;
 241
 242         /* Check main VCO clock source: eosc, intosc or f2s? */
 243         switch (main_cfg->vco0_psrc) {
 244         case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
 245                 clk_hz = eosc1_hz;
 246                 break;
 247         case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
 248                 clk_hz = cb_intosc_hz;
 249                 break;
 250         case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
 251                 clk_hz = f2s_free_hz;
 252                 break;
 253         default:
 254                 return 0;
 255         }
 256
 257         /* calculate the VCO frequency */
 258         clk_hz /= 1 + main_cfg->vco1_denom;
 259         clk_hz *= 1 + main_cfg->vco1_numer;
 260
 261         return clk_hz;
 262 }
 263
 264 /* calculate the intended periph VCO frequency based on handoff */
 265 static unsigned int cm_calc_handoff_periph_vco_clk_hz(
 266                 struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 267 {
 268         unsigned int clk_hz;
 269
 270         /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */
 271         switch (per_cfg->vco0_psrc) {
 272         case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
 273                 clk_hz = eosc1_hz;
 274                 break;
 275         case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
 276                 clk_hz = cb_intosc_hz;
 277                 break;
 278         case CLKMGR_PERPLL_VCO0_PSRC_F2S:
 279                 clk_hz = f2s_free_hz;
 280                 break;
 281         case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
 282                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 283                 clk_hz /= main_cfg->cntr15clk_cnt;
 284                 break;
 285         default:
 286                 return 0;
 287         }
 288
 289         /* calculate the VCO frequency */
 290         clk_hz /= 1 + per_cfg->vco1_denom;
 291         clk_hz *= 1 + per_cfg->vco1_numer;
 292
 293         return clk_hz;
 294 }
 295
 296 /* calculate the intended MPU clock frequency based on handoff */
 297 static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg,
 298                                                struct perpll_cfg *per_cfg)
 299 {
 300         unsigned int clk_hz;
 301
 302         /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
 303         switch (main_cfg->mpuclk_src) {
 304         case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
 305                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 306                 clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK)
 307                            + 1;
 308                 break;
 309         case CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
 310                 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
 311                 clk_hz /= ((main_cfg->mpuclk >>
 312                            CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
 313                            CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
 314                 break;
 315         case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
 316                 clk_hz = eosc1_hz;
 317                 break;
 318         case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
 319                 clk_hz = cb_intosc_hz;
 320                 break;
 321         case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
 322                 clk_hz = f2s_free_hz;
 323                 break;
 324         default:
 325                 return 0;
 326         }
 327
 328         clk_hz /= main_cfg->mpuclk_cnt + 1;
 329         return clk_hz;
 330 }
 331
 332 /* calculate the intended NOC clock frequency based on handoff */
 333 static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg,
 334                                                struct perpll_cfg *per_cfg)
 335 {
 336         unsigned int clk_hz;
 337
 338         /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
 339         switch (main_cfg->nocclk_src) {
 340         case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN:
 341                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 342                 clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK)
 343                          + 1;
 344                 break;
 345         case CLKMGR_MAINPLL_NOCCLK_SRC_PERI:
 346                 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
 347                 clk_hz /= ((main_cfg->nocclk >>
 348                            CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
 349                            CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1;
 350                 break;
 351         case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1:
 352                 clk_hz = eosc1_hz;
 353                 break;
 354         case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC:
 355                 clk_hz = cb_intosc_hz;
 356                 break;
 357         case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA:
 358                 clk_hz = f2s_free_hz;
 359                 break;
 360         default:
 361                 return 0;
 362         }
 363
 364         clk_hz /= main_cfg->nocclk_cnt + 1;
 365         return clk_hz;
 366 }
 367
 368 /* return 1 if PLL ramp is required */
 369 static int cm_is_pll_ramp_required(int main0periph1,
 370                                    struct mainpll_cfg *main_cfg,
 371                                    struct perpll_cfg *per_cfg)
 372 {
 373         /* Check for main PLL */
 374         if (main0periph1 == 0) {
 375                 /*
 376                  * PLL ramp is not required if both MPU clock and NOC clock are
 377                  * not sourced from main PLL
 378                  */
 379                 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
 380                     main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
 381                         return 0;
 382
 383                 /*
 384                  * PLL ramp is required if MPU clock is sourced from main PLL
 385                  * and MPU clock is over 900MHz (as advised by HW team)
 386                  */
 387                 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
 388                     (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
 389                      CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
 390                         return 1;
 391
 392                 /*
 393                  * PLL ramp is required if NOC clock is sourced from main PLL
 394                  * and NOC clock is over 300MHz (as advised by HW team)
 395                  */
 396                 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN &&
 397                     (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
 398                      CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
 399                         return 2;
 400
 401         } else if (main0periph1 == 1) {
 402                 /*
 403                  * PLL ramp is not required if both MPU clock and NOC clock are
 404                  * not sourced from periph PLL
 405                  */
 406                 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
 407                     main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
 408                         return 0;
 409
 410                 /*
 411                  * PLL ramp is required if MPU clock are source from periph PLL
 412                  * and MPU clock is over 900MHz (as advised by HW team)
 413                  */
 414                 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
 415                     (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
 416                      CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
 417                         return 1;
 418
 419                 /*
 420                  * PLL ramp is required if NOC clock are source from periph PLL
 421                  * and NOC clock is over 300MHz (as advised by HW team)
 422                  */
 423                 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI &&
 424                     (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
 425                      CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
 426                         return 2;
 427         }
 428
 429         return 0;
 430 }
 431
 432 static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg,
 433                               struct perpll_cfg *per_cfg,
 434                               u32 safe_hz, u32 clk_hz)
 435 {
 436         u32 cnt;
 437         u32 clk;
 438         u32 shift;
 439         u32 mask;
 440         u32 denom;
 441
 442         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
 443                 cnt = main_cfg->mpuclk_cnt;
 444                 clk = main_cfg->mpuclk;
 445                 shift = 0;
 446                 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
 447                 denom = main_cfg->vco1_denom;
 448         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
 449                 cnt = main_cfg->nocclk_cnt;
 450                 clk = main_cfg->nocclk;
 451                 shift = 0;
 452                 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
 453                 denom = main_cfg->vco1_denom;
 454         } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
 455                 cnt = main_cfg->mpuclk_cnt;
 456                 clk = main_cfg->mpuclk;
 457                 shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB;
 458                 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
 459                 denom = per_cfg->vco1_denom;
 460         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
 461                 cnt = main_cfg->nocclk_cnt;
 462                 clk = main_cfg->nocclk;
 463                 shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB;
 464                 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
 465                 denom = per_cfg->vco1_denom;
 466         } else {
 467                 return 0;
 468         }
 469
 470         return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) *
 471                 (1 + denom) - 1;
 472 }
 473
 474 /*
 475  * Calculate the new PLL numerator which is based on existing DTS hand off and
 476  * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the
 477  * numerator while maintaining denominator as denominator will influence the
 478  * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final
 479  * value for numerator is minus with 1 to cater our register value
 480  * representation.
 481  */
 482 static unsigned int cm_calc_safe_pll_numer(int main0periph1,
 483                                            struct mainpll_cfg *main_cfg,
 484                                            struct perpll_cfg *per_cfg,
 485                                            unsigned int safe_hz)
 486 {
 487         unsigned int clk_hz = 0;
 488
 489         /* Check for main PLL */
 490         if (main0periph1 == 0) {
 491                 /* Check main VCO clock source: eosc, intosc or f2s? */
 492                 switch (main_cfg->vco0_psrc) {
 493                 case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
 494                         clk_hz = eosc1_hz;
 495                         break;
 496                 case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
 497                         clk_hz = cb_intosc_hz;
 498                         break;
 499                 case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
 500                         clk_hz = f2s_free_hz;
 501                         break;
 502                 default:
 503                         return 0;
 504                 }
 505         } else if (main0periph1 == 1) {
 506                 /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */
 507                 switch (per_cfg->vco0_psrc) {
 508                 case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
 509                         clk_hz = eosc1_hz;
 510                         break;
 511                 case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
 512                         clk_hz = cb_intosc_hz;
 513                         break;
 514                 case CLKMGR_PERPLL_VCO0_PSRC_F2S:
 515                         clk_hz = f2s_free_hz;
 516                         break;
 517                 case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
 518                         clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 519                         clk_hz /= main_cfg->cntr15clk_cnt;
 520                         break;
 521                 default:
 522                         return 0;
 523                 }
 524         } else {
 525                 return 0;
 526         }
 527
 528         return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz);
 529 }
 530
 531 /* ramping the main PLL to final value */
 532 static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
 533                              struct perpll_cfg *per_cfg,
 534                              unsigned int pll_ramp_main_hz)
 535 {
 536         unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
 537
 538         /* find out the increment value */
 539         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
 540                 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
 541                 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
 542         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
 543                 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
 544                 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
 545         }
 546
 547         /* execute the ramping here */
 548         for (clk_hz = pll_ramp_main_hz + clk_incr_hz;
 549              clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
 550                 writel((main_cfg->vco1_denom <<
 551                         CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 552                         cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
 553                         socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 554                 mdelay(1);
 555                 cm_wait_for_lock(LOCKED_MASK);
 556         }
 557         writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 558                 main_cfg->vco1_numer,
 559                 socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 560         mdelay(1);
 561         cm_wait_for_lock(LOCKED_MASK);
 562 }
 563
 564 /* ramping the periph PLL to final value */
 565 static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
 566                                struct perpll_cfg *per_cfg,
 567                                unsigned int pll_ramp_periph_hz)
 568 {
 569         unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
 570
 571         /* find out the increment value */
 572         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
 573                 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
 574                 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
 575         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
 576                 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
 577                 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
 578         }
 579         /* execute the ramping here */
 580         for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
 581              clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
 582                 writel((per_cfg->vco1_denom <<
 583                               CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 584                               cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
 585                                                      clk_hz),
 586                               socfpga_get_clkmgr_addr() +
 587                               CLKMGR_A10_PERPLL_VCO1);
 588                 mdelay(1);
 589                 cm_wait_for_lock(LOCKED_MASK);
 590         }
 591         writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 592                       per_cfg->vco1_numer,
 593                       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 594         mdelay(1);
 595         cm_wait_for_lock(LOCKED_MASK);
 596 }
 597
 598 /*
 599  * Setup clocks while making no assumptions of the
 600  * previous state of the clocks.
 601  *
 602  * Start by being paranoid and gate all sw managed clocks
 603  *
 604  * Put all plls in bypass
 605  *
 606  * Put all plls VCO registers back to reset value (bgpwr dwn).
 607  *
 608  * Put peripheral and main pll src to reset value to avoid glitch.
 609  *
 610  * Delay 5 us.
 611  *
 612  * Deassert bg pwr dn and set numerator and denominator
 613  *
 614  * Start 7 us timer.
 615  *
 616  * set internal dividers
 617  *
 618  * Wait for 7 us timer.
 619  *
 620  * Enable plls
 621  *
 622  * Set external dividers while plls are locking
 623  *
 624  * Wait for pll lock
 625  *
 626  * Assert/deassert outreset all.
 627  *
 628  * Take all pll's out of bypass
 629  *
 630  * Clear safe mode
 631  *
 632  * set source main and peripheral clocks
 633  *
 634  * Ungate clocks
 635  */
 636
 637 static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 638 {
 639         unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0,
 640                 ramp_required;
 641
 642         /* gate off all mainpll clock excpet HW managed clock */
 643         writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
 644                 CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
 645                 socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENR);
 646
 647         /* now we can gate off the rest of the peripheral clocks */
 648         writel(0, socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EN);
 649
 650         /* Put all plls in external bypass */
 651         writel(CLKMGR_MAINPLL_BYPASS_RESET,
 652                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSS);
 653         writel(CLKMGR_PERPLL_BYPASS_RESET,
 654                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSS);
 655
 656         /*
 657          * Put all plls VCO registers back to reset value.
 658          * Some code might have messed with them. At same time set the
 659          * desired clock source
 660          */
 661         writel(CLKMGR_MAINPLL_VCO0_RESET |
 662                CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
 663                (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB),
 664                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0);
 665
 666         writel(CLKMGR_PERPLL_VCO0_RESET |
 667                CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
 668                (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),
 669                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0);
 670
 671         writel(CLKMGR_MAINPLL_VCO1_RESET,
 672                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 673         writel(CLKMGR_PERPLL_VCO1_RESET,
 674                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 675
 676         /* clear the interrupt register status register */
 677         writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
 678                 CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
 679                 CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
 680                 CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
 681                 CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
 682                 CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
 683                 CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
 684                 CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
 685                 socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR);
 686
 687         /* Program VCO Numerator and Denominator for main PLL */
 688         ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);
 689         if (ramp_required) {
 690                 /* set main PLL to safe starting threshold frequency */
 691                 if (ramp_required == 1)
 692                         pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
 693                 else if (ramp_required == 2)
 694                         pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 695
 696                 writel((main_cfg->vco1_denom <<
 697                         CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 698                         cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
 699                                                pll_ramp_main_hz),
 700                         socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 701         } else
 702                 writel((main_cfg->vco1_denom <<
 703                        CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 704                        main_cfg->vco1_numer,
 705                        socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 706
 707         /* Program VCO Numerator and Denominator for periph PLL */
 708         ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);
 709         if (ramp_required) {
 710                 /* set periph PLL to safe starting threshold frequency */
 711                 if (ramp_required == 1)
 712                         pll_ramp_periph_hz =
 713                                 CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
 714                 else if (ramp_required == 2)
 715                         pll_ramp_periph_hz =
 716                                 CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 717
 718                 writel((per_cfg->vco1_denom <<
 719                         CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 720                         cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
 721                                                pll_ramp_periph_hz),
 722                         socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 723         } else
 724                 writel((per_cfg->vco1_denom <<
 725                         CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 726                         per_cfg->vco1_numer,
 727                         socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 728
 729         /* Wait for at least 5 us */
 730         udelay(5);
 731
 732         /* Now deassert BGPWRDN and PWRDN */
 733         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
 734                      CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
 735                      CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
 736         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
 737                      CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
 738                      CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
 739
 740         /* Wait for at least 7 us */
 741         udelay(7);
 742
 743         /* enable the VCO and disable the external regulator to PLL */
 744         writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
 745                 ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
 746                 CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
 747                 socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0);
 748         writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0) &
 749                 ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
 750                 CLKMGR_PERPLL_VCO0_EN_SET_MSK,
 751                 socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0);
 752
 753         /* setup all the main PLL counter and clock source */
 754         writel(main_cfg->nocclk,
 755                socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_NOCCLK);
 756         writel(main_cfg->mpuclk,
 757                socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_MPUCLK);
 758
 759         /* main_emaca_clk divider */
 760         writel(main_cfg->cntr2clk_cnt,
 761                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR2CLK);
 762         /* main_emacb_clk divider */
 763         writel(main_cfg->cntr3clk_cnt,
 764                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR3CLK);
 765         /* main_emac_ptp_clk divider */
 766         writel(main_cfg->cntr4clk_cnt,
 767                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR4CLK);
 768         /* main_gpio_db_clk divider */
 769         writel(main_cfg->cntr5clk_cnt,
 770                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR5CLK);
 771         /* main_sdmmc_clk divider */
 772         writel(main_cfg->cntr6clk_cnt,
 773                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR6CLK);
 774         /* main_s2f_user0_clk divider */
 775         writel(main_cfg->cntr7clk_cnt |
 776                (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
 777                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR7CLK);
 778         /* main_s2f_user1_clk divider */
 779         writel(main_cfg->cntr8clk_cnt,
 780                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR8CLK);
 781         /* main_hmc_pll_clk divider */
 782         writel(main_cfg->cntr9clk_cnt |
 783                (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
 784                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR9CLK);
 785         /* main_periph_ref_clk divider */
 786         writel(main_cfg->cntr15clk_cnt,
 787                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR15CLK);
 788
 789         /* setup all the peripheral PLL counter and clock source */
 790         /* peri_emaca_clk divider */
 791         writel(per_cfg->cntr2clk_cnt |
 792                (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
 793                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR2CLK);
 794         /* peri_emacb_clk divider */
 795         writel(per_cfg->cntr3clk_cnt |
 796                (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
 797                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR3CLK);
 798         /* peri_emac_ptp_clk divider */
 799         writel(per_cfg->cntr4clk_cnt |
 800                (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
 801                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR4CLK);
 802         /* peri_gpio_db_clk divider */
 803         writel(per_cfg->cntr5clk_cnt |
 804                (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
 805                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR5CLK);
 806         /* peri_sdmmc_clk divider */
 807         writel(per_cfg->cntr6clk_cnt |
 808                (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
 809                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR6CLK);
 810         /* peri_s2f_user0_clk divider */
 811         writel(per_cfg->cntr7clk_cnt,
 812                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR7CLK);
 813         /* peri_s2f_user1_clk divider */
 814         writel(per_cfg->cntr8clk_cnt |
 815                (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
 816                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR8CLK);
 817         /* peri_hmc_pll_clk divider */
 818         writel(per_cfg->cntr9clk_cnt,
 819                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR9CLK);
 820
 821         /* setup all the external PLL counter */
 822         /* mpu wrapper / external divider */
 823         writel(main_cfg->mpuclk_cnt |
 824                (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
 825                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_MPUCLK);
 826         /* NOC wrapper / external divider */
 827         writel(main_cfg->nocclk_cnt |
 828                (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
 829                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCCLK);
 830         /* NOC subclock divider such as l4 */
 831         writel(main_cfg->nocdiv_l4mainclk |
 832                (main_cfg->nocdiv_l4mpclk <<
 833                 CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) |
 834                (main_cfg->nocdiv_l4spclk <<
 835                 CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) |
 836                (main_cfg->nocdiv_csatclk <<
 837                 CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) |
 838                (main_cfg->nocdiv_cstraceclk <<
 839                 CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
 840                (main_cfg->nocdiv_cspdbclk <<
 841                 CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
 842                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCDIV);
 843         /* gpio_db external divider */
 844         writel(per_cfg->gpiodiv_gpiodbclk,
 845                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_GPIOFIV);
 846
 847         /* setup the EMAC clock mux select */
 848         writel((per_cfg->emacctl_emac0sel <<
 849                 CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) |
 850                (per_cfg->emacctl_emac1sel <<
 851                 CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
 852                (per_cfg->emacctl_emac2sel <<
 853                 CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
 854                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EMACCTL);
 855
 856         /* at this stage, check for PLL lock status */
 857         cm_wait_for_lock(LOCKED_MASK);
 858
 859         /*
 860          * after locking, but before taking out of bypass,
 861          * assert/deassert outresetall
 862          */
 863         /* assert mainpll outresetall */
 864         setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
 865                      CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
 866         /* assert perpll outresetall */
 867         setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
 868                      CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
 869         /* de-assert mainpll outresetall */
 870         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
 871                      CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
 872         /* de-assert perpll outresetall */
 873         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
 874                      CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
 875
 876         /* Take all PLLs out of bypass when boot mode is cleared. */
 877         /* release mainpll from bypass */
 878         writel(CLKMGR_MAINPLL_BYPASS_RESET,
 879                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR);
 880         /* wait till Clock Manager is not busy */
 881         cm_wait_for_fsm();
 882
 883         /* release perpll from bypass */
 884         writel(CLKMGR_PERPLL_BYPASS_RESET,
 885                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR);
 886         /* wait till Clock Manager is not busy */
 887         cm_wait_for_fsm();
 888
 889         /* clear boot mode */
 890         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
 891                      CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
 892         /* wait till Clock Manager is not busy */
 893         cm_wait_for_fsm();
 894
 895         /* At here, we need to ramp to final value if needed */
 896         if (pll_ramp_main_hz != 0)
 897                 cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz);
 898         if (pll_ramp_periph_hz != 0)
 899                 cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz);
 900
 901         /* Now ungate non-hw-managed clocks */
 902         writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
 903                CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
 904                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENS);
 905         writel(CLKMGR_PERPLL_EN_RESET,
 906                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_ENS);
 907
 908         /* Clear the loss lock and slip bits as they might set during
 909         clock reconfiguration */
 910         writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
 911                CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
 912                CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
 913                CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
 914                CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
 915                CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
 916                socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR);
 917
 918         return 0;
 919 }
 920
 921 static void cm_use_intosc(void)
 922 {
 923         setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
 924                      CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
 925 }
 926
 927 int cm_basic_init(const void *blob)
 928 {
 929         struct mainpll_cfg main_cfg;
 930         struct perpll_cfg per_cfg;
 931         int rval;
 932
 933         /* initialize to zero for use case of optional node */
 934         memset(&main_cfg, 0, sizeof(main_cfg));
 935         memset(&per_cfg, 0, sizeof(per_cfg));
 936
 937         rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg);
 938         if (rval)
 939                 return rval;
 940
 941         cm_use_intosc();
 942
 943         return cm_full_cfg(&main_cfg, &per_cfg);
 944 }
 945 #endif
 946
 947 static u32 cm_get_rate_dm(char *name)
 948 {
 949         struct uclass *uc;
 950         struct udevice *dev = NULL;
 951         struct clk clk = { 0 };
 952         ulong rate;
 953         int ret;
 954
 955         /* Device addresses start at 1 */
 956         ret = uclass_get(UCLASS_CLK, &uc);
 957         if (ret)
 958                 return 0;
 959
 960         ret = uclass_get_device_by_name(UCLASS_CLK, name, &dev);
 961         if (ret)
 962                 return 0;
 963
 964         ret = device_probe(dev);
 965         if (ret)
 966                 return 0;
 967
 968         ret = clk_request(dev, &clk);
 969         if (ret)
 970                 return 0;
 971
 972         rate = clk_get_rate(&clk);
 973
 974         clk_free(&clk);
 975
 976         return rate;
 977 }
 978
 979 static u32 cm_get_rate_dm_khz(char *name)
 980 {
 981         return cm_get_rate_dm(name) / 1000;
 982 }
 983
 984 unsigned long cm_get_mpu_clk_hz(void)
 985 {
 986         return cm_get_rate_dm("main_mpu_base_clk");
 987 }
 988
 989 unsigned int cm_get_qspi_controller_clk_hz(void)
 990 {
 991         return cm_get_rate_dm("qspi_clk");
 992 }
 993
 994 unsigned int cm_get_l4_sp_clk_hz(void)
 995 {
 996         return cm_get_rate_dm("l4_sp_clk");
 997 }
 998
 999 void cm_print_clock_quick_summary(void)
1000 {
1001         printf("MPU       %10d kHz\n", cm_get_rate_dm_khz("main_mpu_base_clk"));
1002         printf("MMC         %8d kHz\n", cm_get_rate_dm_khz("sdmmc_clk"));
1003         printf("QSPI        %8d kHz\n", cm_get_rate_dm_khz("qspi_clk"));
1004         printf("SPI         %8d kHz\n", cm_get_rate_dm_khz("spi_m_clk"));
1005         printf("EOSC1       %8d kHz\n", cm_get_rate_dm_khz("osc1"));
1006         printf("cb_intosc   %8d kHz\n", cm_get_rate_dm_khz("cb_intosc_ls_clk"));
1007         printf("f2s_free    %8d kHz\n", cm_get_rate_dm_khz("f2s_free_clk"));
1008         printf("Main VCO    %8d kHz\n", cm_get_rate_dm_khz("main_pll@40"));
1009         printf("NOC         %8d kHz\n", cm_get_rate_dm_khz("main_noc_base_clk"));
1010         printf("L4 Main     %8d kHz\n", cm_get_rate_dm_khz("l4_main_clk"));
1011         printf("L4 MP       %8d kHz\n", cm_get_rate_dm_khz("l4_mp_clk"));
1012         printf("L4 SP       %8d kHz\n", cm_get_rate_dm_khz("l4_sp_clk"));
1013         printf("L4 sys free %8d kHz\n", cm_get_rate_dm_khz("l4_sys_free_clk"));
1014 }