1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
11 #include <asm/arch/clock_manager.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 void cm_wait_for_lock(u32 mask)
20 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
21 inter_val = readl(socfpga_get_clkmgr_addr() +
24 inter_val = readl(socfpga_get_clkmgr_addr() +
27 /* Wait for stable lock */
28 if (inter_val == mask)
37 /* function to poll in the fsm busy bit */
38 int cm_wait_for_fsm(void)
40 return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
41 CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
45 int set_cpu_clk_info(void)
47 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
48 /* Calculate the clock frequencies required for drivers */
49 cm_get_l4_sp_clk_hz();
50 cm_get_mmc_controller_clk_hz();
53 gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
54 gd->bd->bi_dsp_freq = 0;
56 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
57 gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
59 gd->bd->bi_ddr_freq = 0;
65 #ifndef CONFIG_SPL_BUILD
66 static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
69 cm_print_clock_quick_summary();
74 clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,