1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
4 * Copyright (c) 2016 Andreas Färber
10 #include <asm/armv8/mmu.h>
12 #include <asm/arch-rockchip/bootrom.h>
13 #include <asm/arch-rockchip/clock.h>
14 #include <asm/arch-rockchip/cru_rk3368.h>
15 #include <asm/arch-rockchip/grf_rk3368.h>
16 #include <asm/arch-rockchip/hardware.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #define IMEM_BASE 0xFF8C0000
24 /* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
25 #define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4)
26 #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
27 #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
28 /* exsram may using by mcu to accessing dram(0x0-0x20000000) */
29 #define MCU_EXSRAM_BASE (0)
30 #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
31 #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
32 /* experi no used, reserved value = 0 */
33 #define MCU_EXPERI_BASE (0)
34 #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
35 #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
37 static struct mm_region rk3368_mem_map[] = {
42 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
48 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
50 PTE_BLOCK_PXN | PTE_BLOCK_UXN
57 struct mm_region *mem_map = rk3368_mem_map;
59 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
60 [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
61 [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
64 #ifdef CONFIG_ARCH_EARLY_INIT_R
65 static int mcu_init(void)
67 struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
68 struct rk3368_cru *cru = rockchip_get_cru();
70 rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
71 MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
72 rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
73 MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
74 rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
75 MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
76 rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
77 MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
78 rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
79 MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
80 rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
81 MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
83 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
84 (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
85 (5 << MCU_CLK_DIV_SHIFT));
87 /* mcu dereset, for start running */
88 rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
93 int arch_early_init_r(void)
99 #ifdef CONFIG_SPL_BUILD
101 * The SPL (and also the full U-Boot stage on the RK3368) will run in
102 * secure mode (i.e. EL3) and an ATF will eventually be booted before
103 * starting up the operating system... so we can initialize the SGRF
104 * here and rely on the ATF installing the final (secure) policy
107 static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
109 const uintptr_t SGRF_BASE =
110 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
112 return SGRF_BASE + sizeof(u32) * no;
115 static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
117 const uintptr_t SGRF_BASE =
118 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
119 const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
120 const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
122 return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
125 static void sgrf_init(void)
127 struct rk3368_cru * const cru =
128 (struct rk3368_cru * const)rockchip_get_cru();
129 const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
130 const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
131 const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
133 /* Set all configurable IP to 'non secure'-mode */
134 rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
135 rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
136 rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
139 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
140 * Original comment: "ddr space set no secure mode"
142 rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
143 rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
144 rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
146 /* Set 'secure dma' to 'non secure'-mode */
147 rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
148 rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
152 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
153 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
158 rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
159 rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
162 int arch_cpu_init(void)
164 /* Reset security, so we can use DMA in the MMC drivers */
171 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
172 void board_debug_uart_init(void)
175 * N.B.: This is called before the device-model has been
176 * initialised. For this reason, we can not access
177 * the GRF address range using the syscon API.
179 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
180 struct rk3368_grf * const grf =
181 (struct rk3368_grf * const)0xff770000;
184 GPIO2D1_MASK = GENMASK(3, 2),
186 GPIO2D1_UART0_SOUT = (1 << 2),
188 GPIO2D0_MASK = GENMASK(1, 0),
190 GPIO2D0_UART0_SIN = (1 << 0),
193 /* Enable early UART0 on the RK3368 */
194 rk_clrsetreg(&grf->gpio2d_iomux,
195 GPIO2D0_MASK, GPIO2D0_UART0_SIN);
196 rk_clrsetreg(&grf->gpio2d_iomux,
197 GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
198 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
199 struct rk3368_pmu_grf * const pmugrf __maybe_unused =
200 (struct rk3368_pmu_grf * const)0xff738000;
204 GPIO0D2_MASK = GENMASK(5, 4),
206 GPIO0D2_UART4_SOUT = (3 << 4),
208 GPIO0D3_MASK = GENMASK(7, 6),
210 GPIO0D3_UART4_SIN = (3 << 6),
213 /* Enable early UART4 on the PX5 */
214 rk_clrsetreg(&pmugrf->gpio0d_iomux,
215 GPIO0D2_MASK | GPIO0D3_MASK,
216 GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
217 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
218 struct rk3368_grf * const grf =
219 (struct rk3368_grf * const)0xff770000;
223 GPIO2A6_MASK = GENMASK(13, 12),
225 GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
228 GPIO2A5_MASK = GENMASK(11, 10),
230 GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
233 /* Enable early UART2 on the RK3368 */
234 rk_clrsetreg(&grf->gpio2a_iomux,
235 GPIO2A6_MASK, GPIO2A6_UART2_SIN);
236 rk_clrsetreg(&grf->gpio2a_iomux,
237 GPIO2A5_MASK, GPIO2A5_UART2_SOUT);