arch/arm/mach-rockchip/rk3328/rk3328.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <init.h>
   8 #include <asm/arch-rockchip/bootrom.h>
   9 #include <asm/arch-rockchip/hardware.h>
  10 #include <asm/arch-rockchip/grf_rk3328.h>
  11 #include <asm/arch-rockchip/uart.h>
  12 #include <asm/armv8/mmu.h>
  13 #include <asm/io.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 #define CRU_BASE                0xFF440000
  18 #define GRF_BASE                0xFF100000
  19 #define UART2_BASE              0xFF130000
  20 #define FW_DDR_CON_REG          0xFF7C0040
  21
  22 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  23         [BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000",
  24         [BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000",
  25 };
  26
  27 static struct mm_region rk3328_mem_map[] = {
  28         {
  29                 .virt = 0x0UL,
  30                 .phys = 0x0UL,
  31                 .size = 0xff000000UL,
  32                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  33                          PTE_BLOCK_INNER_SHARE
  34         }, {
  35                 .virt = 0xff000000UL,
  36                 .phys = 0xff000000UL,
  37                 .size = 0x1000000UL,
  38                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  39                          PTE_BLOCK_NON_SHARE |
  40                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  41         }, {
  42                 /* List terminator */
  43                 0,
  44         }
  45 };
  46
  47 struct mm_region *mem_map = rk3328_mem_map;
  48
  49 int arch_cpu_init(void)
  50 {
  51 #ifdef CONFIG_SPL_BUILD
  52         /* We do some SoC one time setting here. */
  53
  54         /* Disable the ddr secure region setting to make it non-secure */
  55         rk_setreg(FW_DDR_CON_REG, 0x200);
  56 #endif
  57         return 0;
  58 }
  59
  60 void board_debug_uart_init(void)
  61 {
  62         struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
  63         struct rk_uart * const uart = (void *)UART2_BASE;
  64         enum{
  65                 GPIO2A0_SEL_SHIFT       = 0,
  66                 GPIO2A0_SEL_MASK        = 3 << GPIO2A0_SEL_SHIFT,
  67                 GPIO2A0_UART2_TX_M1     = 1,
  68
  69                 GPIO2A1_SEL_SHIFT       = 2,
  70                 GPIO2A1_SEL_MASK        = 3 << GPIO2A1_SEL_SHIFT,
  71                 GPIO2A1_UART2_RX_M1     = 1,
  72         };
  73         enum {
  74                 IOMUX_SEL_UART2_SHIFT   = 0,
  75                 IOMUX_SEL_UART2_MASK    = 3 << IOMUX_SEL_UART2_SHIFT,
  76                 IOMUX_SEL_UART2_M0      = 0,
  77                 IOMUX_SEL_UART2_M1,
  78         };
  79
  80         /* uart_sel_clk default select 24MHz */
  81         writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
  82
  83         /* init uart baud rate 1500000 */
  84         writel(0x83, &uart->lcr);
  85         writel(0x1, &uart->rbr);
  86         writel(0x3, &uart->lcr);
  87
  88         /* Enable early UART2 */
  89         rk_clrsetreg(&grf->com_iomux,
  90                      IOMUX_SEL_UART2_MASK,
  91                      IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
  92         rk_clrsetreg(&grf->gpio2a_iomux,
  93                      GPIO2A0_SEL_MASK,
  94                      GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
  95         rk_clrsetreg(&grf->gpio2a_iomux,
  96                      GPIO2A1_SEL_MASK,
  97                      GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
  98
  99         /* enable FIFO */
 100         writel(0x1, &uart->sfe);
 101 }