arch/arm/mach-rockchip/rk3308/rk3308.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *Copyright (c) 2018 Rockchip Electronics Co., Ltd
   4  */
   5 #include <common.h>
   6 #include <init.h>
   7 #include <malloc.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/grf_rk3308.h>
  10 #include <asm/arch-rockchip/hardware.h>
  11 #include <asm/gpio.h>
  12 #include <debug_uart.h>
  13 #include <linux/bitops.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 #include <asm/armv8/mmu.h>
  18 static struct mm_region rk3308_mem_map[] = {
  19         {
  20                 .virt = 0x0UL,
  21                 .phys = 0x0UL,
  22                 .size = 0xff000000UL,
  23                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  24                          PTE_BLOCK_INNER_SHARE
  25         }, {
  26                 .virt = 0xff000000UL,
  27                 .phys = 0xff000000UL,
  28                 .size = 0x01000000UL,
  29                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  30                          PTE_BLOCK_NON_SHARE |
  31                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  32         }, {
  33                 /* List terminator */
  34                 0,
  35         }
  36 };
  37
  38 struct mm_region *mem_map = rk3308_mem_map;
  39
  40 #define GRF_BASE        0xff000000
  41 #define SGRF_BASE       0xff2b0000
  42
  43 enum {
  44         GPIO1C7_SHIFT           = 8,
  45         GPIO1C7_MASK            = GENMASK(11, 8),
  46         GPIO1C7_GPIO            = 0,
  47         GPIO1C7_UART1_RTSN,
  48         GPIO1C7_UART2_TX_M0,
  49         GPIO1C7_SPI2_MOSI,
  50         GPIO1C7_JTAG_TMS,
  51
  52         GPIO1C6_SHIFT           = 4,
  53         GPIO1C6_MASK            = GENMASK(7, 4),
  54         GPIO1C6_GPIO            = 0,
  55         GPIO1C6_UART1_CTSN,
  56         GPIO1C6_UART2_RX_M0,
  57         GPIO1C6_SPI2_MISO,
  58         GPIO1C6_JTAG_TCLK,
  59
  60         GPIO4D3_SHIFT           = 6,
  61         GPIO4D3_MASK            = GENMASK(7, 6),
  62         GPIO4D3_GPIO            = 0,
  63         GPIO4D3_SDMMC_D3,
  64         GPIO4D3_UART2_TX_M1,
  65
  66         GPIO4D2_SHIFT           = 4,
  67         GPIO4D2_MASK            = GENMASK(5, 4),
  68         GPIO4D2_GPIO            = 0,
  69         GPIO4D2_SDMMC_D2,
  70         GPIO4D2_UART2_RX_M1,
  71
  72         UART2_IO_SEL_SHIFT      = 2,
  73         UART2_IO_SEL_MASK       = GENMASK(3, 2),
  74         UART2_IO_SEL_M0         = 0,
  75         UART2_IO_SEL_M1,
  76         UART2_IO_SEL_USB,
  77
  78         GPIO2C0_SEL_SRC_CTRL_SHIFT      = 11,
  79         GPIO2C0_SEL_SRC_CTRL_MASK       = BIT(11),
  80         GPIO2C0_SEL_SRC_CTRL_IOMUX      = 0,
  81         GPIO2C0_SEL_SRC_CTRL_SEL_PLUS,
  82
  83         GPIO3B3_SEL_SRC_CTRL_SHIFT      = 7,
  84         GPIO3B3_SEL_SRC_CTRL_MASK       = BIT(7),
  85         GPIO3B3_SEL_SRC_CTRL_IOMUX      = 0,
  86         GPIO3B3_SEL_SRC_CTRL_SEL_PLUS,
  87
  88         GPIO3B3_SEL_PLUS_SHIFT          = 4,
  89         GPIO3B3_SEL_PLUS_MASK           = GENMASK(6, 4),
  90         GPIO3B3_SEL_PLUS_GPIO3_B3       = 0,
  91         GPIO3B3_SEL_PLUS_FLASH_ALE,
  92         GPIO3B3_SEL_PLUS_EMMC_PWREN,
  93         GPIO3B3_SEL_PLUS_SPI1_CLK,
  94         GPIO3B3_SEL_PLUS_LCDC_D23_M1,
  95
  96         GPIO3B2_SEL_SRC_CTRL_SHIFT      = 3,
  97         GPIO3B2_SEL_SRC_CTRL_MASK       = BIT(3),
  98         GPIO3B2_SEL_SRC_CTRL_IOMUX      = 0,
  99         GPIO3B2_SEL_SRC_CTRL_SEL_PLUS,
 100
 101         GPIO3B2_SEL_PLUS_SHIFT          = 0,
 102         GPIO3B2_SEL_PLUS_MASK           = GENMASK(2, 0),
 103         GPIO3B2_SEL_PLUS_GPIO3_B2       = 0,
 104         GPIO3B2_SEL_PLUS_FLASH_RDN,
 105         GPIO3B2_SEL_PLUS_EMMC_RSTN,
 106         GPIO3B2_SEL_PLUS_SPI1_MISO,
 107         GPIO3B2_SEL_PLUS_LCDC_D22_M1,
 108
 109         I2C3_IOFUNC_SRC_CTRL_SHIFT      = 10,
 110         I2C3_IOFUNC_SRC_CTRL_MASK       = BIT(10),
 111         I2C3_IOFUNC_SRC_CTRL_SEL_PLUS   = 1,
 112
 113         GPIO2A3_SEL_SRC_CTRL_SHIFT      = 7,
 114         GPIO2A3_SEL_SRC_CTRL_MASK       = BIT(7),
 115         GPIO2A3_SEL_SRC_CTRL_SEL_PLUS   = 1,
 116
 117         GPIO2A2_SEL_SRC_CTRL_SHIFT      = 3,
 118         GPIO2A2_SEL_SRC_CTRL_MASK       = BIT(3),
 119         GPIO2A2_SEL_SRC_CTRL_SEL_PLUS   = 1,
 120 };
 121
 122 enum {
 123         IOVSEL3_CTRL_SHIFT      = 8,
 124         IOVSEL3_CTRL_MASK       = BIT(8),
 125         VCCIO3_SEL_BY_GPIO      = 0,
 126         VCCIO3_SEL_BY_IOVSEL3,
 127
 128         IOVSEL3_SHIFT           = 3,
 129         IOVSEL3_MASK            = BIT(3),
 130         VCCIO3_3V3              = 0,
 131         VCCIO3_1V8,
 132 };
 133
 134 /*
 135  * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc
 136  * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults
 137  * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware,
 138  * then we can switch to io_vsel3 after system power on, and release GPIO0_A4
 139  * for other usage.
 140  */
 141
 142 #define GPIO0_A4        4
 143
 144 int rk_board_init(void)
 145 {
 146         static struct rk3308_grf * const grf = (void *)GRF_BASE;
 147         u32 val;
 148         int ret;
 149
 150         ret = gpio_request(GPIO0_A4, "gpio0_a4");
 151         if (ret < 0) {
 152                 printf("request for gpio0_a4 failed:%d\n", ret);
 153                 return 0;
 154         }
 155
 156         gpio_direction_input(GPIO0_A4);
 157
 158         if (gpio_get_value(GPIO0_A4))
 159                 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
 160                       VCCIO3_1V8 << IOVSEL3_SHIFT;
 161         else
 162                 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
 163                       VCCIO3_3V3 << IOVSEL3_SHIFT;
 164         rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val);
 165
 166         gpio_free(GPIO0_A4);
 167         return 0;
 168 }
 169
 170 #if defined(CONFIG_DEBUG_UART)
 171 __weak void board_debug_uart_init(void)
 172 {
 173         static struct rk3308_grf * const grf = (void *)GRF_BASE;
 174
 175         /* Enable early UART2 channel m1 on the rk3308 */
 176         rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
 177                      UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
 178         rk_clrsetreg(&grf->gpio4d_iomux,
 179                      GPIO4D3_MASK | GPIO4D2_MASK,
 180                      GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT |
 181                      GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT);
 182 }
 183 #endif
 184
 185 #if defined(CONFIG_SPL_BUILD)
 186 int arch_cpu_init(void)
 187 {
 188         static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
 189         static struct rk3308_grf * const grf = (void *)GRF_BASE;
 190
 191         /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
 192         rk_clrreg(&sgrf->con_secure0, 0x2b83);
 193
 194         /*
 195          * Enable plus options to use more pinctrl functions, including
 196          * GPIO2A2_PLUS, GPIO2A3_PLUS and I2C3_MULTI_SRC_PLUS.
 197          */
 198         rk_clrsetreg(&grf->soc_con13,
 199                      I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK |
 200                      GPIO2A2_SEL_SRC_CTRL_MASK,
 201                      I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << I2C3_IOFUNC_SRC_CTRL_SHIFT |
 202                      GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << GPIO2A3_SEL_SRC_CTRL_SHIFT |
 203                      GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << GPIO2A2_SEL_SRC_CTRL_SHIFT);
 204
 205         /* Plus options about GPIO3B2_PLUS, GPIO3B3_PLUS and GPIO2C0_PLUS. */
 206         rk_clrsetreg(&grf->soc_con15,
 207                      GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK |
 208                      GPIO3B2_SEL_SRC_CTRL_MASK,
 209                      GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << GPIO2C0_SEL_SRC_CTRL_SHIFT |
 210                      GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B3_SEL_SRC_CTRL_SHIFT |
 211                      GPIO3B2_SEL_SRC_CTRL_SEL_PLUS << GPIO3B2_SEL_SRC_CTRL_SHIFT);
 212
 213         return 0;
 214 }
 215 #endif