arch/arm/mach-rockchip/rk3288/rk3288.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
   4  */
   5 #include <common.h>
   6 #include <command.h>
   7 #include <dm.h>
   8 #include <env.h>
   9 #include <clk.h>
  10 #include <init.h>
  11 #include <malloc.h>
  12 #include <asm/armv7.h>
  13 #include <asm/io.h>
  14 #include <asm/arch-rockchip/bootrom.h>
  15 #include <asm/arch-rockchip/clock.h>
  16 #include <asm/arch-rockchip/cru.h>
  17 #include <asm/arch-rockchip/hardware.h>
  18 #include <asm/arch-rockchip/grf_rk3288.h>
  19 #include <asm/arch-rockchip/pmu_rk3288.h>
  20 #include <asm/arch-rockchip/qos_rk3288.h>
  21 #include <asm/arch-rockchip/sdram.h>
  22 #include <linux/err.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define GRF_BASE        0xff770000
  27
  28 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  29         [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
  30         [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
  31 };
  32
  33 #ifdef CONFIG_SPL_BUILD
  34 static void configure_l2ctlr(void)
  35 {
  36         u32 l2ctlr;
  37
  38         l2ctlr = read_l2ctlr();
  39         l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
  40
  41         /*
  42          * Data RAM write latency: 2 cycles
  43          * Data RAM read latency: 2 cycles
  44          * Data RAM setup latency: 1 cycle
  45          * Tag RAM write latency: 1 cycle
  46          * Tag RAM read latency: 1 cycle
  47          * Tag RAM setup latency: 1 cycle
  48          */
  49         l2ctlr |= (1 << 3 | 1 << 0);
  50         write_l2ctlr(l2ctlr);
  51 }
  52 #endif
  53
  54 int rk3288_qos_init(void)
  55 {
  56         int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
  57         /* set vop qos to higher priority */
  58         writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
  59         writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
  60
  61         if (!fdt_node_check_compatible(gd->fdt_blob, 0,
  62                                        "rockchip,rk3288-tinker")) {
  63                 /* set isp qos to higher priority */
  64                 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
  65                 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
  66                 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
  67         }
  68
  69         return 0;
  70 }
  71
  72 int arch_cpu_init(void)
  73 {
  74 #ifdef CONFIG_SPL_BUILD
  75         configure_l2ctlr();
  76 #else
  77         /* We do some SoC one time setting here. */
  78         struct rk3288_grf * const grf = (void *)GRF_BASE;
  79
  80         /* Use rkpwm by default */
  81         rk_setreg(&grf->soc_con2, 1 << 0);
  82
  83         /*
  84          * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
  85          * cleared
  86          */
  87         rk_clrreg(&grf->soc_con0, 1 << 12);
  88
  89         rk3288_qos_init();
  90 #endif
  91
  92         return 0;
  93 }
  94
  95 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  96 void board_debug_uart_init(void)
  97 {
  98         /* Enable early UART on the RK3288 */
  99         struct rk3288_grf * const grf = (void *)GRF_BASE;
 100
 101         rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
 102                      GPIO7C6_MASK << GPIO7C6_SHIFT,
 103                      GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
 104                      GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 105 }
 106 #endif
 107
 108 __weak int rk3288_board_late_init(void)
 109 {
 110         return 0;
 111 }
 112
 113 int rk_board_late_init(void)
 114 {
 115         return rk3288_board_late_init();
 116 }
 117
 118 static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc,
 119                     char *const argv[])
 120 {
 121         static const struct {
 122                 char *name;
 123                 int id;
 124         } clks[] = {
 125                 { "osc", CLK_OSC },
 126                 { "apll", CLK_ARM },
 127                 { "dpll", CLK_DDR },
 128                 { "cpll", CLK_CODEC },
 129                 { "gpll", CLK_GENERAL },
 130 #ifdef CONFIG_ROCKCHIP_RK3036
 131                 { "mpll", CLK_NEW },
 132 #else
 133                 { "npll", CLK_NEW },
 134 #endif
 135         };
 136         int ret, i;
 137         struct udevice *dev;
 138
 139         ret = rockchip_get_clk(&dev);
 140         if (ret) {
 141                 printf("clk-uclass not found\n");
 142                 return 0;
 143         }
 144
 145         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 146                 struct clk clk;
 147                 ulong rate;
 148
 149                 clk.id = clks[i].id;
 150                 ret = clk_request(dev, &clk);
 151                 if (ret < 0)
 152                         continue;
 153
 154                 rate = clk_get_rate(&clk);
 155                 printf("%s: %lu\n", clks[i].name, rate);
 156
 157                 clk_free(&clk);
 158         }
 159
 160         return 0;
 161 }
 162
 163 U_BOOT_CMD(
 164         clock, 2, 1, do_clock,
 165         "display information about clocks",
 166         ""
 167 );