arch/arm/mach-rockchip/px30/px30.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017 Rockchip Electronics Co., Ltd
   4  */
   5 #include <common.h>
   6 #include <clk.h>
   7 #include <dm.h>
   8 #include <init.h>
   9 #include <asm/armv8/mmu.h>
  10 #include <asm/io.h>
  11 #include <asm/arch-rockchip/grf_px30.h>
  12 #include <asm/arch-rockchip/hardware.h>
  13 #include <asm/arch-rockchip/uart.h>
  14 #include <asm/arch-rockchip/clock.h>
  15 #include <asm/arch-rockchip/cru_px30.h>
  16 #include <dt-bindings/clock/px30-cru.h>
  17
  18 static struct mm_region px30_mem_map[] = {
  19         {
  20                 .virt = 0x0UL,
  21                 .phys = 0x0UL,
  22                 .size = 0xff000000UL,
  23                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  24                          PTE_BLOCK_INNER_SHARE
  25         }, {
  26                 .virt = 0xff000000UL,
  27                 .phys = 0xff000000UL,
  28                 .size = 0x01000000UL,
  29                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  30                          PTE_BLOCK_NON_SHARE |
  31                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  32         }, {
  33                 /* List terminator */
  34                 0,
  35         }
  36 };
  37
  38 struct mm_region *mem_map = px30_mem_map;
  39
  40 #define PMU_PWRDN_CON                   0xff000018
  41 #define PMUGRF_BASE                     0xff010000
  42 #define GRF_BASE                        0xff140000
  43 #define CRU_BASE                        0xff2b0000
  44 #define VIDEO_PHY_BASE                  0xff2e0000
  45 #define SERVICE_CORE_ADDR               0xff508000
  46 #define DDR_FW_BASE                     0xff534000
  47
  48 #define FW_DDR_CON                      0x40
  49
  50 #define QOS_PRIORITY                    0x08
  51
  52 #define QOS_PRIORITY_LEVEL(h, l)        ((((h) & 3) << 8) | ((l) & 3))
  53
  54 /* GRF_GPIO1BH_IOMUX */
  55 enum {
  56         GPIO1B7_SHIFT           = 12,
  57         GPIO1B7_MASK            = 0xf << GPIO1B7_SHIFT,
  58         GPIO1B7_GPIO            = 0,
  59         GPIO1B7_FLASH_RDN,
  60         GPIO1B7_UART3_RXM1,
  61         GPIO1B7_SPI0_CLK,
  62
  63         GPIO1B6_SHIFT           = 8,
  64         GPIO1B6_MASK            = 0xf << GPIO1B6_SHIFT,
  65         GPIO1B6_GPIO            = 0,
  66         GPIO1B6_FLASH_CS1,
  67         GPIO1B6_UART3_TXM1,
  68         GPIO1B6_SPI0_CSN,
  69 };
  70
  71 /* GRF_GPIO1CL_IOMUX */
  72 enum {
  73         GPIO1C1_SHIFT           = 4,
  74         GPIO1C1_MASK            = 0xf << GPIO1C1_SHIFT,
  75         GPIO1C1_GPIO            = 0,
  76         GPIO1C1_UART1_TX,
  77
  78         GPIO1C0_SHIFT           = 0,
  79         GPIO1C0_MASK            = 0xf << GPIO1C0_SHIFT,
  80         GPIO1C0_GPIO            = 0,
  81         GPIO1C0_UART1_RX,
  82 };
  83
  84 /* GRF_GPIO1DL_IOMUX */
  85 enum {
  86         GPIO1D3_SHIFT           = 12,
  87         GPIO1D3_MASK            = 0xf << GPIO1D3_SHIFT,
  88         GPIO1D3_GPIO            = 0,
  89         GPIO1D3_SDMMC_D1,
  90         GPIO1D3_UART2_RXM0,
  91
  92         GPIO1D2_SHIFT           = 8,
  93         GPIO1D2_MASK            = 0xf << GPIO1D2_SHIFT,
  94         GPIO1D2_GPIO            = 0,
  95         GPIO1D2_SDMMC_D0,
  96         GPIO1D2_UART2_TXM0,
  97 };
  98
  99 /* GRF_GPIO1DH_IOMUX */
 100 enum {
 101         GPIO1D7_SHIFT           = 12,
 102         GPIO1D7_MASK            = 0xf << GPIO1D7_SHIFT,
 103         GPIO1D7_GPIO            = 0,
 104         GPIO1D7_SDMMC_CMD,
 105
 106         GPIO1D6_SHIFT           = 8,
 107         GPIO1D6_MASK            = 0xf << GPIO1D6_SHIFT,
 108         GPIO1D6_GPIO            = 0,
 109         GPIO1D6_SDMMC_CLK,
 110
 111         GPIO1D5_SHIFT           = 4,
 112         GPIO1D5_MASK            = 0xf << GPIO1D5_SHIFT,
 113         GPIO1D5_GPIO            = 0,
 114         GPIO1D5_SDMMC_D3,
 115
 116         GPIO1D4_SHIFT           = 0,
 117         GPIO1D4_MASK            = 0xf << GPIO1D4_SHIFT,
 118         GPIO1D4_GPIO            = 0,
 119         GPIO1D4_SDMMC_D2,
 120 };
 121
 122 /* GRF_GPIO2BH_IOMUX */
 123 enum {
 124         GPIO2B6_SHIFT           = 8,
 125         GPIO2B6_MASK            = 0xf << GPIO2B6_SHIFT,
 126         GPIO2B6_GPIO            = 0,
 127         GPIO2B6_CIF_D1M0,
 128         GPIO2B6_UART2_RXM1,
 129
 130         GPIO2B4_SHIFT           = 0,
 131         GPIO2B4_MASK            = 0xf << GPIO2B4_SHIFT,
 132         GPIO2B4_GPIO            = 0,
 133         GPIO2B4_CIF_D0M0,
 134         GPIO2B4_UART2_TXM1,
 135 };
 136
 137 /* GRF_GPIO3AL_IOMUX */
 138 enum {
 139         GPIO3A2_SHIFT           = 8,
 140         GPIO3A2_MASK            = 0xf << GPIO3A2_SHIFT,
 141         GPIO3A2_GPIO            = 0,
 142         GPIO3A2_UART5_TX        = 4,
 143
 144         GPIO3A1_SHIFT           = 4,
 145         GPIO3A1_MASK            = 0xf << GPIO3A1_SHIFT,
 146         GPIO3A1_GPIO            = 0,
 147         GPIO3A1_UART5_RX        = 4,
 148 };
 149
 150 /* PMUGRF_GPIO0CL_IOMUX */
 151 enum {
 152         GPIO0C1_SHIFT           = 2,
 153         GPIO0C1_MASK            = 0x3 << GPIO0C1_SHIFT,
 154         GPIO0C1_GPIO            = 0,
 155         GPIO0C1_PWM_3,
 156         GPIO0C1_UART3_RXM0,
 157         GPIO0C1_PMU_DEBUG4,
 158
 159         GPIO0C0_SHIFT           = 0,
 160         GPIO0C0_MASK            = 0x3 << GPIO0C0_SHIFT,
 161         GPIO0C0_GPIO            = 0,
 162         GPIO0C0_PWM_1,
 163         GPIO0C0_UART3_TXM0,
 164         GPIO0C0_PMU_DEBUG3,
 165 };
 166
 167 int arch_cpu_init(void)
 168 {
 169         static struct px30_grf * const grf = (void *)GRF_BASE;
 170         u32 __maybe_unused val;
 171
 172 #ifdef CONFIG_SPL_BUILD
 173         /* We do some SoC one time setting here. */
 174         /* Disable the ddr secure region setting to make it non-secure */
 175         writel(0x0, DDR_FW_BASE + FW_DDR_CON);
 176
 177         /* Set cpu qos priority */
 178         writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY);
 179
 180 #if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \
 181         (CONFIG_DEBUG_UART_BASE != 0xff160000) || \
 182         (CONFIG_DEBUG_UART_CHANNEL != 0)
 183         /* fix sdmmc pinmux if not using uart2-channel0 as debug uart */
 184         rk_clrsetreg(&grf->gpio1dl_iomux,
 185                      GPIO1D3_MASK | GPIO1D2_MASK,
 186                      GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT |
 187                      GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT);
 188         rk_clrsetreg(&grf->gpio1dh_iomux,
 189                      GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK,
 190                      GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT |
 191                      GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT |
 192                      GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT |
 193                      GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
 194 #endif
 195
 196 #endif
 197
 198         /* Enable PD_VO (default disable at reset) */
 199         rk_clrreg(PMU_PWRDN_CON, 1 << 13);
 200
 201         /* Disable video phy bandgap by default */
 202         writel(0x82, VIDEO_PHY_BASE + 0x0000);
 203         writel(0x05, VIDEO_PHY_BASE + 0x03ac);
 204
 205         /* Clear the force_jtag */
 206         rk_clrreg(&grf->cpu_con[1], 1 << 7);
 207
 208         return 0;
 209 }
 210
 211 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 212 void board_debug_uart_init(void)
 213 {
 214 #if defined(CONFIG_DEBUG_UART_BASE) && \
 215         (CONFIG_DEBUG_UART_BASE == 0xff168000) && \
 216         (CONFIG_DEBUG_UART_CHANNEL != 1)
 217         static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
 218 #endif
 219         static struct px30_grf * const grf = (void *)GRF_BASE;
 220         static struct px30_cru * const cru = (void *)CRU_BASE;
 221
 222 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)
 223         /* uart_sel_clk default select 24MHz */
 224         rk_clrsetreg(&cru->clksel_con[34],
 225                      UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK,
 226                      UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0);
 227         rk_clrsetreg(&cru->clksel_con[35],
 228                      UART1_CLK_SEL_MASK,
 229                      UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT);
 230
 231         rk_clrsetreg(&grf->gpio1cl_iomux,
 232                      GPIO1C1_MASK | GPIO1C0_MASK,
 233                      GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
 234                      GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
 235 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff168000)
 236         /* GRF_IOFUNC_CON0 */
 237         enum {
 238                 CON_IOMUX_UART3SEL_SHIFT        = 9,
 239                 CON_IOMUX_UART3SEL_MASK = 1 << CON_IOMUX_UART3SEL_SHIFT,
 240                 CON_IOMUX_UART3SEL_M0   = 0,
 241                 CON_IOMUX_UART3SEL_M1,
 242         };
 243
 244         /* uart_sel_clk default select 24MHz */
 245         rk_clrsetreg(&cru->clksel_con[40],
 246                      UART3_PLL_SEL_MASK | UART3_DIV_CON_MASK,
 247                      UART3_PLL_SEL_24M << UART3_PLL_SEL_SHIFT | 0);
 248         rk_clrsetreg(&cru->clksel_con[41],
 249                      UART3_CLK_SEL_MASK,
 250                      UART3_CLK_SEL_UART3 << UART3_CLK_SEL_SHIFT);
 251
 252 #if (CONFIG_DEBUG_UART_CHANNEL == 1)
 253         rk_clrsetreg(&grf->iofunc_con0,
 254                      CON_IOMUX_UART3SEL_MASK,
 255                      CON_IOMUX_UART3SEL_M1 << CON_IOMUX_UART3SEL_SHIFT);
 256
 257         rk_clrsetreg(&grf->gpio1bh_iomux,
 258                      GPIO1B7_MASK | GPIO1B6_MASK,
 259                      GPIO1B7_UART3_RXM1 << GPIO1B7_SHIFT |
 260                      GPIO1B6_UART3_TXM1 << GPIO1B6_SHIFT);
 261 #else
 262         rk_clrsetreg(&grf->iofunc_con0,
 263                      CON_IOMUX_UART3SEL_MASK,
 264                      CON_IOMUX_UART3SEL_M0 << CON_IOMUX_UART3SEL_SHIFT);
 265
 266         rk_clrsetreg(&pmugrf->gpio0cl_iomux,
 267                      GPIO0C1_MASK | GPIO0C0_MASK,
 268                      GPIO0C1_UART3_RXM0 << GPIO0C1_SHIFT |
 269                      GPIO0C0_UART3_TXM0 << GPIO0C0_SHIFT);
 270 #endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */
 271
 272 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
 273         /* uart_sel_clk default select 24MHz */
 274         rk_clrsetreg(&cru->clksel_con[46],
 275                      UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK,
 276                      UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0);
 277         rk_clrsetreg(&cru->clksel_con[47],
 278                      UART5_CLK_SEL_MASK,
 279                      UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT);
 280
 281         rk_clrsetreg(&grf->gpio3al_iomux,
 282                      GPIO3A2_MASK | GPIO3A1_MASK,
 283                      GPIO3A2_UART5_TX << GPIO3A2_SHIFT |
 284                      GPIO3A1_UART5_RX << GPIO3A1_SHIFT);
 285 #else
 286         /* GRF_IOFUNC_CON0 */
 287         enum {
 288                 CON_IOMUX_UART2SEL_SHIFT        = 10,
 289                 CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT,
 290                 CON_IOMUX_UART2SEL_M0   = 0,
 291                 CON_IOMUX_UART2SEL_M1,
 292                 CON_IOMUX_UART2SEL_USBPHY,
 293         };
 294
 295         /* uart_sel_clk default select 24MHz */
 296         rk_clrsetreg(&cru->clksel_con[37],
 297                      UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK,
 298                      UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0);
 299         rk_clrsetreg(&cru->clksel_con[38],
 300                      UART2_CLK_SEL_MASK,
 301                      UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT);
 302
 303 #if (CONFIG_DEBUG_UART_CHANNEL == 1)
 304         /* Enable early UART2 */
 305         rk_clrsetreg(&grf->iofunc_con0,
 306                      CON_IOMUX_UART2SEL_MASK,
 307                      CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT);
 308
 309         rk_clrsetreg(&grf->gpio2bh_iomux,
 310                      GPIO2B6_MASK | GPIO2B4_MASK,
 311                      GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT |
 312                      GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT);
 313 #else
 314         rk_clrsetreg(&grf->iofunc_con0,
 315                      CON_IOMUX_UART2SEL_MASK,
 316                      CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT);
 317
 318         rk_clrsetreg(&grf->gpio1dl_iomux,
 319                      GPIO1D3_MASK | GPIO1D2_MASK,
 320                      GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT |
 321                      GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT);
 322 #endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */
 323
 324 #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
 325 }
 326 #endif /* CONFIG_DEBUG_UART_BOARD_INIT */