1 // SPDX-License-Identifier: GPL-2.0+
4 * Common functions for OMAP4/5 based boards
7 * Texas Instruments, <www.ti.com>
10 * Aneesh V <aneesh@ti.com>
11 * Steve Sakoman <steve@sakoman.com>
17 #include <asm/cache.h>
19 DECLARE_GLOBAL_DATA_PTR;
22 * Without LPAE short descriptors are used
25 * The last 2 bits set to 0b10
29 * With LPAE cache configuration happens via MAIR0 register
30 * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
31 * 0xFF maps to Cache writeback with Read and Write Allocate set
32 * The bits[1:0] should have the value 0b01 for the first level
37 #ifdef CONFIG_ARMV7_LPAE
38 #define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
40 #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
43 #define ARMV7_DOMAIN_CLIENT 1
44 #define ARMV7_DOMAIN_MASK (0x3 << 0)
46 void enable_caches(void)
49 /* Enable I cache if not enabled */
56 void dram_bank_mmu_setup(int bank)
61 u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
62 u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
63 u32 end = start + size;
65 debug("%s: bank: %d\n", __func__, bank);
66 for (i = start; i < end; i++)
67 set_section_dcache(i, ARMV7_DCACHE_POLICY);
70 void arm_init_domains(void)
76 * Set DOMAIN to client access so that all permissions
77 * set in pagetables are validated by the mmu.
79 reg &= ~ARMV7_DOMAIN_MASK;
80 reg |= ARMV7_DOMAIN_CLIENT;