1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
10 #include <asm/arch/boot.h>
11 #include <asm/arch/eth.h>
12 #include <asm/arch/gx.h>
13 #include <asm/arch/mem.h>
14 #include <asm/arch/meson-vpu.h>
16 #include <asm/armv8/mmu.h>
17 #include <linux/sizes.h>
19 #include <linux/usb/otg.h>
20 #include <asm/arch/usb-gx.h>
21 #include <usb/dwc2_udc.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 int meson_get_boot_device(void)
29 return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
32 /* Configure the reserved memory zones exported by the secure registers
33 * into EFI and DTB reserved memory entries.
35 void meson_init_reserved_memory(void *fdt)
37 u64 bl31_size, bl31_start;
38 u64 bl32_size, bl32_start;
42 * Get ARM Trusted Firmware reserved memory zones in :
43 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
44 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
45 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
47 reg = readl(GX_AO_SEC_GP_CFG3);
49 bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
50 >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
51 bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
53 bl31_start = readl(GX_AO_SEC_GP_CFG5);
54 bl32_start = readl(GX_AO_SEC_GP_CFG4);
57 * Early Meson GX Firmware revisions did not provide the reserved
58 * memory zones in the registers, keep fixed memory zone handling.
60 if (IS_ENABLED(CONFIG_MESON_GX) &&
61 !reg && !bl31_start && !bl32_start) {
62 bl31_start = 0x10000000;
66 /* Add first 16MiB reserved zone */
67 meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
69 /* Add BL31 reserved zone */
70 if (bl31_start && bl31_size)
71 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
73 /* Add BL32 reserved zone */
74 if (bl32_start && bl32_size)
75 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
77 #if defined(CONFIG_VIDEO_MESON)
78 meson_vpu_rsv_fb(fdt);
82 phys_size_t get_effective_memsize(void)
84 /* Size is reported in MiB, convert it in bytes */
85 return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
86 >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
89 static struct mm_region gx_mem_map[] = {
94 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
100 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
101 PTE_BLOCK_NON_SHARE |
102 PTE_BLOCK_PXN | PTE_BLOCK_UXN
104 /* List terminator */
109 struct mm_region *mem_map = gx_mem_map;
111 /* Configure the Ethernet MAC with the requested interface mode
112 * with some optional flags.
114 void meson_eth_init(phy_interface_t mode, unsigned int flags)
117 case PHY_INTERFACE_MODE_RGMII:
118 case PHY_INTERFACE_MODE_RGMII_ID:
119 case PHY_INTERFACE_MODE_RGMII_RXID:
120 case PHY_INTERFACE_MODE_RGMII_TXID:
122 setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
123 GX_ETH_REG_0_TX_PHASE(1) |
124 GX_ETH_REG_0_TX_RATIO(4) |
125 GX_ETH_REG_0_PHY_CLK_EN |
126 GX_ETH_REG_0_CLK_EN);
128 /* Reset to external PHY */
129 if(!IS_ENABLED(CONFIG_MESON_GXBB))
130 writel(0x2009087f, GX_ETH_REG_3);
134 case PHY_INTERFACE_MODE_RMII:
136 out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
137 GX_ETH_REG_0_CLK_EN);
139 /* Use GXL RMII Internal PHY (also on GXM) */
140 if (!IS_ENABLED(CONFIG_MESON_GXBB)) {
141 if ((flags & MESON_USE_INTERNAL_RMII_PHY)) {
142 writel(0x10110181, GX_ETH_REG_2);
143 writel(0xe40908ff, GX_ETH_REG_3);
145 writel(0x2009087f, GX_ETH_REG_3);
151 printf("Invalid Ethernet interface mode\n");
155 /* Enable power gate */
156 clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
159 #if CONFIG_IS_ENABLED(USB_XHCI_DWC3_OF_SIMPLE) && \
160 CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
161 static struct dwc2_plat_otg_data meson_gx_dwc2_data;
162 static struct phy usb_phys[2];
164 int board_usb_init(int index, enum usb_init_type init)
166 struct ofnode_phandle_args args;
167 struct udevice *clk_dev;
173 /* find the dwc2 node */
174 dwc2_node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
175 if (!ofnode_valid(dwc2_node)) {
176 debug("Not found dwc2 node\n");
180 if (!ofnode_is_available(dwc2_node)) {
181 debug("dwc2 is disabled in the device tree\n");
186 for (i = 0; i < 2; i++) {
187 ret = generic_phy_get_by_index_nodev(dwc2_node, i,
189 if (ret && ret != -ENOENT) {
190 pr_err("Failed to get USB PHY%d for %s\n",
191 i, ofnode_get_name(dwc2_node));
196 for (i = 0; i < 2; i++) {
197 ret = generic_phy_init(&usb_phys[i]);
199 pr_err("Can't init USB PHY%d for %s\n",
200 i, ofnode_get_name(dwc2_node));
205 for (i = 0; i < 2; i++) {
206 ret = generic_phy_power_on(&usb_phys[i]);
208 pr_err("Can't power USB PHY%d for %s\n",
209 i, ofnode_get_name(dwc2_node));
214 phy_meson_gxl_usb3_set_mode(&usb_phys[0], USB_DR_MODE_PERIPHERAL);
215 phy_meson_gxl_usb2_set_mode(&usb_phys[1], USB_DR_MODE_PERIPHERAL);
217 meson_gx_dwc2_data.regs_otg = ofnode_get_addr(dwc2_node);
218 if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
219 debug("usbotg: can't get base address\n");
224 ret = ofnode_parse_phandle_with_args(dwc2_node, "clocks",
225 "#clock-cells", 0, 0, &args);
227 debug("usbotg has no clocks defined in the device tree\n");
231 ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &clk_dev);
235 if (args.args_count != 1) {
236 debug("Can't find clock ID in the device tree\n");
241 clk.id = args.args[0];
243 ret = clk_enable(&clk);
245 debug("Failed to enable usbotg clock\n");
249 ofnode_read_u32(dwc2_node, "g-rx-fifo-size", &val);
250 meson_gx_dwc2_data.rx_fifo_sz = val;
251 ofnode_read_u32(dwc2_node, "g-np-tx-fifo-size", &val);
252 meson_gx_dwc2_data.np_tx_fifo_sz = val;
253 ofnode_read_u32(dwc2_node, "g-tx-fifo-size", &val);
254 meson_gx_dwc2_data.tx_fifo_sz = val;
256 return dwc2_udc_probe(&meson_gx_dwc2_data);
259 int board_usb_cleanup(int index, enum usb_init_type init)
263 phy_meson_gxl_usb3_set_mode(&usb_phys[0], USB_DR_MODE_HOST);
264 phy_meson_gxl_usb2_set_mode(&usb_phys[1], USB_DR_MODE_HOST);
266 for (i = 0; i < 2; i++)
267 usb_phys[i].dev = NULL;