1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
10 #include <asm/arch/boot.h>
11 #include <asm/arch/eth.h>
12 #include <asm/arch/axg.h>
13 #include <asm/arch/mem.h>
15 #include <asm/armv8/mmu.h>
16 #include <linux/sizes.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 int meson_get_boot_device(void)
23 return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
26 /* Configure the reserved memory zones exported by the secure registers
27 * into EFI and DTB reserved memory entries.
29 void meson_init_reserved_memory(void *fdt)
31 u64 bl31_size, bl31_start;
32 u64 bl32_size, bl32_start;
36 * Get ARM Trusted Firmware reserved memory zones in :
37 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
38 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
39 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
41 reg = readl(AXG_AO_SEC_GP_CFG3);
43 bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
44 >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
45 bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
47 bl31_start = readl(AXG_AO_SEC_GP_CFG5);
48 bl32_start = readl(AXG_AO_SEC_GP_CFG4);
50 /* Add BL31 reserved zone */
51 if (bl31_start && bl31_size)
52 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
54 /* Add BL32 reserved zone */
55 if (bl32_start && bl32_size)
56 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
59 phys_size_t get_effective_memsize(void)
61 /* Size is reported in MiB, convert it in bytes */
62 return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
63 >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
66 static struct mm_region axg_mem_map[] = {
71 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
77 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
79 PTE_BLOCK_PXN | PTE_BLOCK_UXN
86 struct mm_region *mem_map = axg_mem_map;
88 /* Configure the Ethernet MAC with the requested interface mode
89 * with some optional flags.
91 void meson_eth_init(phy_interface_t mode, unsigned int flags)
94 case PHY_INTERFACE_MODE_RGMII:
95 case PHY_INTERFACE_MODE_RGMII_ID:
96 case PHY_INTERFACE_MODE_RGMII_RXID:
97 case PHY_INTERFACE_MODE_RGMII_TXID:
99 setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
100 AXG_ETH_REG_0_TX_PHASE(1) |
101 AXG_ETH_REG_0_TX_RATIO(4) |
102 AXG_ETH_REG_0_PHY_CLK_EN |
103 AXG_ETH_REG_0_CLK_EN);
106 case PHY_INTERFACE_MODE_RMII:
108 out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
109 AXG_ETH_REG_0_INVERT_RMII_CLK |
110 AXG_ETH_REG_0_CLK_EN);
114 printf("Invalid Ethernet interface mode\n");
118 /* Enable power gate */
119 clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);