arch/arm/mach-mediatek/mt8512/init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Configuration for MediaTek MT8512 SoC
   4  *
   5  * Copyright (C) 2019 MediaTek Inc.
   6  * Author: Mingming Lee <mingming.lee@mediatek.com>
   7  */
   8
   9 #include <clk.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <fdtdec.h>
  13 #include <init.h>
  14 #include <log.h>
  15 #include <ram.h>
  16 #include <wdt.h>
  17 #include <asm/arch/misc.h>
  18 #include <asm/armv8/mmu.h>
  19 #include <asm/cache.h>
  20 #include <asm/sections.h>
  21 #include <dm/uclass.h>
  22 #include <dt-bindings/clock/mt8512-clk.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 int dram_init(void)
  27 {
  28         return fdtdec_setup_mem_size_base();
  29 }
  30
  31 phys_size_t  get_effective_memsize(void)
  32 {
  33         /* limit stack below tee reserve memory */
  34         return gd->ram_size - 6 * SZ_1M;
  35 }
  36
  37 int dram_init_banksize(void)
  38 {
  39         gd->bd->bi_dram[0].start = gd->ram_base;
  40         gd->bd->bi_dram[0].size = get_effective_memsize();
  41
  42         return 0;
  43 }
  44
  45 void reset_cpu(ulong addr)
  46 {
  47         struct udevice *watchdog_dev = NULL;
  48
  49         if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev))
  50                 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev))
  51                         psci_system_reset();
  52
  53         wdt_expire_now(watchdog_dev, 0);
  54 }
  55
  56 int print_cpuinfo(void)
  57 {
  58         debug("CPU:   MediaTek MT8512\n");
  59         return 0;
  60 }
  61
  62 static struct mm_region mt8512_mem_map[] = {
  63         {
  64                 /* DDR */
  65                 .virt = 0x40000000UL,
  66                 .phys = 0x40000000UL,
  67                 .size = 0x40000000UL,
  68                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
  69         }, {
  70                 .virt = 0x00000000UL,
  71                 .phys = 0x00000000UL,
  72                 .size = 0x40000000UL,
  73                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  74                          PTE_BLOCK_NON_SHARE |
  75                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  76         }, {
  77                 0,
  78         }
  79 };
  80
  81 struct mm_region *mem_map = mt8512_mem_map;