arch/arm/mach-mediatek/mt7629/init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 MediaTek Inc.
   4  * Author: Ryder Lee <ryder.lee@mediatek.com>
   5  */
   6
   7 #include <clk.h>
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <ram.h>
  14 #include <asm/arch/misc.h>
  15 #include <asm/sections.h>
  16 #include <dm/uclass.h>
  17 #include <linux/bitops.h>
  18 #include <linux/io.h>
  19
  20 #include <dt-bindings/clock/mt7629-clk.h>
  21
  22 #define L2_CFG_BASE             0x10200000
  23 #define L2_CFG_SIZE             0x1000
  24 #define L2_SHARE_CFG_MP0        0x7f0
  25 #define L2_SHARE_MODE_OFF       BIT(8)
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int mtk_pll_early_init(void)
  30 {
  31         unsigned long pll_rates[] = {
  32                 [CLK_APMIXED_ARMPLL] = 1250000000,
  33                 [CLK_APMIXED_MAINPLL] = 1120000000,
  34                 [CLK_APMIXED_UNIV2PLL] = 1200000000,
  35                 [CLK_APMIXED_ETH1PLL] = 500000000,
  36                 [CLK_APMIXED_ETH2PLL] = 700000000,
  37                 [CLK_APMIXED_SGMIPLL] = 650000000,
  38         };
  39         struct udevice *dev;
  40         int ret, i;
  41
  42         ret = uclass_get_device_by_driver(UCLASS_CLK,
  43                         DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
  44         if (ret)
  45                 return ret;
  46
  47         /* configure default rate then enable apmixedsys */
  48         for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
  49                 struct clk clk = { .id = i, .dev = dev };
  50
  51                 ret = clk_set_rate(&clk, pll_rates[i]);
  52                 if (ret)
  53                         return ret;
  54
  55                 ret = clk_enable(&clk);
  56                 if (ret)
  57                         return ret;
  58         }
  59
  60         /* setup mcu bus */
  61         ret = uclass_get_device_by_driver(UCLASS_SYSCON,
  62                         DM_GET_DRIVER(mtk_mcucfg), &dev);
  63         if (ret)
  64                 return ret;
  65
  66         return 0;
  67 }
  68
  69 int mtk_soc_early_init(void)
  70 {
  71         struct udevice *dev;
  72         int ret;
  73
  74         /* initialize early clocks */
  75         ret = mtk_pll_early_init();
  76         if (ret)
  77                 return ret;
  78
  79         ret = uclass_first_device_err(UCLASS_RAM, &dev);
  80         if (ret)
  81                 return ret;
  82
  83         return 0;
  84 }
  85
  86 int mach_cpu_init(void)
  87 {
  88         void __iomem *base;
  89
  90         base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
  91
  92         /* disable L2C shared mode */
  93         writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
  94
  95         return 0;
  96 }
  97
  98 int dram_init(void)
  99 {
 100         struct ram_info ram;
 101         struct udevice *dev;
 102         int ret;
 103
 104         ret = uclass_first_device_err(UCLASS_RAM, &dev);
 105         if (ret)
 106                 return ret;
 107
 108         ret = ram_get_info(dev, &ram);
 109         if (ret)
 110                 return ret;
 111
 112         debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
 113
 114         gd->ram_size = ram.size;
 115
 116         return 0;
 117 }
 118
 119 int print_cpuinfo(void)
 120 {
 121         void __iomem *chipid;
 122         u32 hwcode, swver;
 123
 124         chipid = ioremap(VER_BASE, VER_SIZE);
 125         hwcode = readl(chipid + APHW_CODE);
 126         swver = readl(chipid + APSW_VER);
 127
 128         printf("CPU:   MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
 129
 130         return 0;
 131 }