arch/arm/mach-keystone/include/mach/hardware-k2hk.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * K2HK: SoC definitions
   4  *
   5  * (C) Copyright 2012-2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
  10 #define __ASM_ARCH_HARDWARE_K2HK_H
  11
  12 #ifndef __ASSEMBLY__
  13 #include <linux/bitops.h>
  14 #endif
  15
  16 #define KS2_ARM_PLL_EN                  BIT(13)
  17
  18 /* PA SS Registers */
  19 #define KS2_PASS_BASE                   0x02000000
  20
  21 /* Power and Sleep Controller (PSC) Domains */
  22 #define KS2_LPSC_MOD                    0
  23 #define KS2_LPSC_DUMMY1                 1
  24 #define KS2_LPSC_USB                    2
  25 #define KS2_LPSC_EMIF25_SPI             3
  26 #define KS2_LPSC_TSIP                   4
  27 #define KS2_LPSC_DEBUGSS_TRC            5
  28 #define KS2_LPSC_TETB_TRC               6
  29 #define KS2_LPSC_PKTPROC                7
  30 #define KS2_LPSC_PA                     KS2_LPSC_PKTPROC
  31 #define KS2_LPSC_SGMII                  8
  32 #define KS2_LPSC_CPGMAC                 KS2_LPSC_SGMII
  33 #define KS2_LPSC_CRYPTO                 9
  34 #define KS2_LPSC_PCIE                   10
  35 #define KS2_LPSC_SRIO                   11
  36 #define KS2_LPSC_VUSR0                  12
  37 #define KS2_LPSC_CHIP_SRSS              13
  38 #define KS2_LPSC_MSMC                   14
  39 #define KS2_LPSC_GEM_1                  16
  40 #define KS2_LPSC_GEM_2                  17
  41 #define KS2_LPSC_GEM_3                  18
  42 #define KS2_LPSC_GEM_4                  19
  43 #define KS2_LPSC_GEM_5                  20
  44 #define KS2_LPSC_GEM_6                  21
  45 #define KS2_LPSC_GEM_7                  22
  46 #define KS2_LPSC_EMIF4F_DDR3A           23
  47 #define KS2_LPSC_EMIF4F_DDR3B           24
  48 #define KS2_LPSC_TAC                    25
  49 #define KS2_LPSC_RAC                    26
  50 #define KS2_LPSC_RAC_1                  27
  51 #define KS2_LPSC_FFTC_A                 28
  52 #define KS2_LPSC_FFTC_B                 29
  53 #define KS2_LPSC_FFTC_C                 30
  54 #define KS2_LPSC_FFTC_D                 31
  55 #define KS2_LPSC_FFTC_E                 32
  56 #define KS2_LPSC_FFTC_F                 33
  57 #define KS2_LPSC_AI2                    34
  58 #define KS2_LPSC_TCP3D_0                35
  59 #define KS2_LPSC_TCP3D_1                36
  60 #define KS2_LPSC_TCP3D_2                37
  61 #define KS2_LPSC_TCP3D_3                38
  62 #define KS2_LPSC_VCP2X4_A               39
  63 #define KS2_LPSC_CP2X4_B                40
  64 #define KS2_LPSC_VCP2X4_C               41
  65 #define KS2_LPSC_VCP2X4_D               42
  66 #define KS2_LPSC_VCP2X4_E               43
  67 #define KS2_LPSC_VCP2X4_F               44
  68 #define KS2_LPSC_VCP2X4_G               45
  69 #define KS2_LPSC_VCP2X4_H               46
  70 #define KS2_LPSC_BCP                    47
  71 #define KS2_LPSC_DXB                    48
  72 #define KS2_LPSC_VUSR1                  49
  73 #define KS2_LPSC_XGE                    50
  74 #define KS2_LPSC_ARM_SREFLEX            51
  75
  76 /* DDR3B definitions */
  77 #define KS2_DDR3B_EMIF_CTRL_BASE        0x21020000
  78 #define KS2_DDR3B_EMIF_DATA_BASE        0x60000000
  79 #define KS2_DDR3B_DDRPHYC               0x02328000
  80
  81 #define KS2_CIC2_DDR3_ECC_IRQ_NUM       0x0D3 /* DDR3 ECC system irq number */
  82 #define KS2_CIC2_DDR3_ECC_CHAN_NUM      0x01D /* DDR3 ECC int mapped to CIC2
  83                                                  channel 29 */
  84
  85 /* SGMII SerDes */
  86 #define KS2_LANES_PER_SGMII_SERDES      4
  87
  88 /* Number of DSP cores */
  89 #define KS2_NUM_DSPS                    8
  90
  91 /* NETCP pktdma */
  92 #define KS2_NETCP_PDMA_CTRL_BASE        0x02004000
  93 #define KS2_NETCP_PDMA_TX_BASE          0x02004400
  94 #define KS2_NETCP_PDMA_TX_CH_NUM        9
  95 #define KS2_NETCP_PDMA_RX_BASE          0x02004800
  96 #define KS2_NETCP_PDMA_RX_CH_NUM        26
  97 #define KS2_NETCP_PDMA_SCHED_BASE       0x02004c00
  98 #define KS2_NETCP_PDMA_RX_FLOW_BASE     0x02005000
  99 #define KS2_NETCP_PDMA_RX_FLOW_NUM      32
 100 #define KS2_NETCP_PDMA_TX_SND_QUEUE     648
 101
 102 /* NETCP */
 103 #define KS2_NETCP_BASE                  0x02000000
 104
 105 #endif /* __ASM_ARCH_HARDWARE_H */