arch/arm/mach-k3/j721e_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * J721E: SoC specific initialization
   4  *
   5  * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <init.h>
  11 #include <spl.h>
  12 #include <asm/io.h>
  13 #include <asm/armv7_mpu.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sysfw-loader.h>
  16 #include "common.h"
  17 #include <asm/arch/sys_proto.h>
  18 #include <linux/soc/ti/ti_sci_protocol.h>
  19 #include <dm.h>
  20 #include <dm/uclass-internal.h>
  21 #include <dm/pinctrl.h>
  22 #include <mmc.h>
  23 #include <remoteproc.h>
  24
  25 #ifdef CONFIG_SPL_BUILD
  26 #ifdef CONFIG_K3_LOAD_SYSFW
  27 #ifdef CONFIG_TI_SECURE_DEVICE
  28 struct fwl_data cbass_hc_cfg0_fwls[] = {
  29         { "PCIE0_CFG", 2560, 8 },
  30         { "PCIE1_CFG", 2561, 8 },
  31         { "USB3SS0_CORE", 2568, 4 },
  32         { "USB3SS1_CORE", 2570, 4 },
  33         { "EMMC8SS0_CFG", 2576, 4 },
  34         { "UFS_HCI0_CFG", 2580, 4 },
  35         { "SERDES0", 2584, 1 },
  36         { "SERDES1", 2585, 1 },
  37 }, cbass_hc0_fwls[] = {
  38         { "PCIE0_HP", 2528, 24 },
  39         { "PCIE0_LP", 2529, 24 },
  40         { "PCIE1_HP", 2530, 24 },
  41         { "PCIE1_LP", 2531, 24 },
  42 }, cbass_rc_cfg0_fwls[] = {
  43         { "EMMCSD4SS0_CFG", 2380, 4 },
  44 }, cbass_rc0_fwls[] = {
  45         { "GPMC0", 2310, 8 },
  46 }, infra_cbass0_fwls[] = {
  47         { "PLL_MMR0", 8, 26 },
  48         { "CTRL_MMR0", 9, 16 },
  49 }, mcu_cbass0_fwls[] = {
  50         { "MCU_R5FSS0_CORE0", 1024, 4 },
  51         { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
  52         { "MCU_R5FSS0_CORE1", 1028, 4 },
  53         { "MCU_FSS0_CFG", 1032, 12 },
  54         { "MCU_FSS0_S1", 1033, 8 },
  55         { "MCU_FSS0_S0", 1036, 8 },
  56         { "MCU_PSROM49152X32", 1048, 1 },
  57         { "MCU_MSRAM128KX64", 1050, 8 },
  58         { "MCU_CTRL_MMR0", 1200, 8 },
  59         { "MCU_PLL_MMR0", 1201, 3 },
  60         { "MCU_CPSW0", 1220, 2 },
  61 }, wkup_cbass0_fwls[] = {
  62         { "WKUP_CTRL_MMR0", 131, 16 },
  63 };
  64 #endif
  65 #endif
  66
  67 static void mmr_unlock(u32 base, u32 partition)
  68 {
  69         /* Translate the base address */
  70         phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  71
  72         /* Unlock the requested partition if locked using two-step sequence */
  73         writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  74         writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  75 }
  76
  77 static void ctrl_mmr_unlock(void)
  78 {
  79         /* Unlock all WKUP_CTRL_MMR0 module registers */
  80         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  81         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  82         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  83         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  84         mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
  85         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  86         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  87
  88         /* Unlock all MCU_CTRL_MMR0 module registers */
  89         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  90         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  91         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  92         mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
  93         mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
  94
  95         /* Unlock all CTRL_MMR0 module registers */
  96         mmr_unlock(CTRL_MMR0_BASE, 0);
  97         mmr_unlock(CTRL_MMR0_BASE, 1);
  98         mmr_unlock(CTRL_MMR0_BASE, 2);
  99         mmr_unlock(CTRL_MMR0_BASE, 3);
 100         mmr_unlock(CTRL_MMR0_BASE, 4);
 101         mmr_unlock(CTRL_MMR0_BASE, 5);
 102         mmr_unlock(CTRL_MMR0_BASE, 6);
 103         mmr_unlock(CTRL_MMR0_BASE, 7);
 104 }
 105
 106 #if defined(CONFIG_K3_LOAD_SYSFW)
 107 void k3_mmc_stop_clock(void)
 108 {
 109         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 110                 struct mmc *mmc = find_mmc_device(0);
 111
 112                 if (!mmc)
 113                         return;
 114
 115                 mmc->saved_clock = mmc->clock;
 116                 mmc_set_clock(mmc, 0, true);
 117         }
 118 }
 119
 120 void k3_mmc_restart_clock(void)
 121 {
 122         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 123                 struct mmc *mmc = find_mmc_device(0);
 124
 125                 if (!mmc)
 126                         return;
 127
 128                 mmc_set_clock(mmc, mmc->saved_clock, false);
 129         }
 130 }
 131 #endif
 132
 133 /*
 134  * This uninitialized global variable would normal end up in the .bss section,
 135  * but the .bss is cleared between writing and reading this variable, so move
 136  * it to the .data section.
 137  */
 138 u32 bootindex __attribute__((section(".data")));
 139
 140 static void store_boot_index_from_rom(void)
 141 {
 142         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
 143 }
 144
 145 void board_init_f(ulong dummy)
 146 {
 147 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
 148         struct udevice *dev;
 149         int ret;
 150 #endif
 151         /*
 152          * Cannot delay this further as there is a chance that
 153          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
 154          */
 155         store_boot_index_from_rom();
 156
 157         /* Make all control module registers accessible */
 158         ctrl_mmr_unlock();
 159
 160 #ifdef CONFIG_CPU_V7R
 161         disable_linefill_optimization();
 162         setup_k3_mpu_regions();
 163 #endif
 164
 165         /* Init DM early */
 166         spl_early_init();
 167
 168 #ifdef CONFIG_K3_LOAD_SYSFW
 169         /*
 170          * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
 171          * regardless of the result of pinctrl. Do this without probing the
 172          * device, but instead by searching the device that would request the
 173          * given sequence number if probed. The UART will be used by the system
 174          * firmware (SYSFW) image for various purposes and SYSFW depends on us
 175          * to initialize its pin settings.
 176          */
 177         ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
 178         if (!ret)
 179                 pinctrl_select_state(dev, "default");
 180
 181         /*
 182          * Load, start up, and configure system controller firmware. Provide
 183          * the U-Boot console init function to the SYSFW post-PM configuration
 184          * callback hook, effectively switching on (or over) the console
 185          * output.
 186          */
 187         k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
 188
 189         /* Prepare console output */
 190         preloader_console_init();
 191
 192         /* Disable ROM configured firewalls right after loading sysfw */
 193 #ifdef CONFIG_TI_SECURE_DEVICE
 194         remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
 195         remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
 196         remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
 197         remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
 198         remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
 199         remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
 200         remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
 201 #endif
 202 #else
 203         /* Prepare console output */
 204         preloader_console_init();
 205 #endif
 206
 207         /* Output System Firmware version info */
 208         k3_sysfw_print_ver();
 209
 210         /* Perform EEPROM-based board detection */
 211         do_board_detect();
 212
 213 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
 214         ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
 215                                           &dev);
 216         if (ret)
 217                 printf("AVS init failed: %d\n", ret);
 218 #endif
 219
 220 #if defined(CONFIG_K3_J721E_DDRSS)
 221         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 222         if (ret)
 223                 panic("DRAM init failed: %d\n", ret);
 224 #endif
 225         spl_enable_dcache();
 226 }
 227
 228 u32 spl_mmc_boot_mode(const u32 boot_device)
 229 {
 230         switch (boot_device) {
 231         case BOOT_DEVICE_MMC1:
 232                 return MMCSD_MODE_EMMCBOOT;
 233         case BOOT_DEVICE_MMC2:
 234                 return MMCSD_MODE_FS;
 235         default:
 236                 return MMCSD_MODE_RAW;
 237         }
 238 }
 239
 240 static u32 __get_backup_bootmedia(u32 main_devstat)
 241 {
 242         u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 243                         MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 244
 245         switch (bkup_boot) {
 246         case BACKUP_BOOT_DEVICE_USB:
 247                 return BOOT_DEVICE_DFU;
 248         case BACKUP_BOOT_DEVICE_UART:
 249                 return BOOT_DEVICE_UART;
 250         case BACKUP_BOOT_DEVICE_ETHERNET:
 251                 return BOOT_DEVICE_ETHERNET;
 252         case BACKUP_BOOT_DEVICE_MMC2:
 253         {
 254                 u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 255                             MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 256                 if (port == 0x0)
 257                         return BOOT_DEVICE_MMC1;
 258                 return BOOT_DEVICE_MMC2;
 259         }
 260         case BACKUP_BOOT_DEVICE_SPI:
 261                 return BOOT_DEVICE_SPI;
 262         case BACKUP_BOOT_DEVICE_I2C:
 263                 return BOOT_DEVICE_I2C;
 264         }
 265
 266         return BOOT_DEVICE_RAM;
 267 }
 268
 269 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
 270 {
 271
 272         u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
 273                         WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
 274
 275         bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
 276                         BOOT_MODE_B_SHIFT;
 277
 278         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 279                 bootmode = BOOT_DEVICE_SPI;
 280
 281         if (bootmode == BOOT_DEVICE_MMC2) {
 282                 u32 port = (main_devstat &
 283                             MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
 284                            MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
 285                 if (port == 0x0)
 286                         bootmode = BOOT_DEVICE_MMC1;
 287         }
 288
 289         return bootmode;
 290 }
 291
 292 u32 spl_boot_device(void)
 293 {
 294         u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
 295         u32 main_devstat;
 296
 297         if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
 298                 printf("ERROR: MCU only boot is not yet supported\n");
 299                 return BOOT_DEVICE_RAM;
 300         }
 301
 302         /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
 303         main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 304
 305         if (bootindex == K3_PRIMARY_BOOTMODE)
 306                 return __get_primary_bootmedia(main_devstat, wkup_devstat);
 307         else
 308                 return __get_backup_bootmedia(main_devstat);
 309 }
 310 #endif
 311
 312 #ifdef CONFIG_SYS_K3_SPL_ATF
 313
 314 #define J721E_DEV_MCU_RTI0                      262
 315 #define J721E_DEV_MCU_RTI1                      263
 316 #define J721E_DEV_MCU_ARMSS0_CPU0               250
 317 #define J721E_DEV_MCU_ARMSS0_CPU1               251
 318
 319 void release_resources_for_core_shutdown(void)
 320 {
 321         struct ti_sci_handle *ti_sci;
 322         struct ti_sci_dev_ops *dev_ops;
 323         struct ti_sci_proc_ops *proc_ops;
 324         int ret;
 325         u32 i;
 326
 327         const u32 put_device_ids[] = {
 328                 J721E_DEV_MCU_RTI0,
 329                 J721E_DEV_MCU_RTI1,
 330         };
 331
 332         ti_sci = get_ti_sci_handle();
 333         dev_ops = &ti_sci->ops.dev_ops;
 334         proc_ops = &ti_sci->ops.proc_ops;
 335
 336         /* Iterate through list of devices to put (shutdown) */
 337         for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
 338                 u32 id = put_device_ids[i];
 339
 340                 ret = dev_ops->put_device(ti_sci, id);
 341                 if (ret)
 342                         panic("Failed to put device %u (%d)\n", id, ret);
 343         }
 344
 345         const u32 put_core_ids[] = {
 346                 J721E_DEV_MCU_ARMSS0_CPU1,
 347                 J721E_DEV_MCU_ARMSS0_CPU0,      /* Handle CPU0 after CPU1 */
 348         };
 349
 350         /* Iterate through list of cores to put (shutdown) */
 351         for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
 352                 u32 id = put_core_ids[i];
 353
 354                 /*
 355                  * Queue up the core shutdown request. Note that this call
 356                  * needs to be followed up by an actual invocation of an WFE
 357                  * or WFI CPU instruction.
 358                  */
 359                 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
 360                 if (ret)
 361                         panic("Failed sending core %u shutdown message (%d)\n",
 362                               id, ret);
 363         }
 364 }
 365 #endif
 366
 367 #ifdef CONFIG_SYS_K3_SPL_ATF
 368 void start_non_linux_remote_cores(void)
 369 {
 370         int size = 0, ret;
 371         u32 loadaddr = 0;
 372
 373         size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
 374                              &loadaddr);
 375         if (size <= 0)
 376                 goto err_load;
 377
 378         /* assuming remoteproc 2 is aliased for the needed remotecore */
 379         ret = rproc_load(2, loadaddr, size);
 380         if (ret) {
 381                 printf("Firmware failed to start on rproc (%d)\n", ret);
 382                 goto err_load;
 383         }
 384
 385         ret = rproc_start(2);
 386         if (ret) {
 387                 printf("Firmware init failed on rproc (%d)\n", ret);
 388                 goto err_load;
 389         }
 390
 391         printf("Remoteproc 2 started successfully\n");
 392
 393         return;
 394
 395 err_load:
 396         rproc_reset(2);
 397 }
 398 #endif