arch/arm/mach-k3/include/mach/j721e_hardware.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * K3: J721E SoC definitions, structures etc.
   4  *
   5  * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7 #ifndef __ASM_ARCH_J721E_HARDWARE_H
   8 #define __ASM_ARCH_J721E_HARDWARE_H
   9
  10 #include <config.h>
  11
  12 #define CTRL_MMR0_BASE                                  0x00100000
  13 #define CTRLMMR_MAIN_DEVSTAT                            (CTRL_MMR0_BASE + 0x30)
  14
  15 #define MAIN_DEVSTAT_BOOT_MODE_B_MASK           BIT(0)
  16 #define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT          0
  17 #define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK         GENMASK(3, 1)
  18 #define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT        1
  19 #define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK        BIT(6)
  20 #define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT           6
  21
  22 #define WKUP_CTRL_MMR0_BASE                             0x43000000
  23 #define MCU_CTRL_MMR0_BASE                              0x40f00000
  24
  25 #define CTRLMMR_WKUP_DEVSTAT                    (WKUP_CTRL_MMR0_BASE + 0x30)
  26 #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK      GENMASK(5, 3)
  27 #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT     3
  28 #define WKUP_DEVSTAT_MCU_OMLY_MASK              BIT(6)
  29 #define WKUP_DEVSTAT_MCU_ONLY_SHIFT             6
  30
  31 /*
  32  * The CTRL_MMR0 memory space is divided into several equally-spaced
  33  * partitions, so defining the partition size allows us to determine
  34  * register addresses common to those partitions.
  35  */
  36 #define CTRL_MMR0_PARTITION_SIZE                        0x4000
  37
  38 /*
  39  * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
  40  * shared register definitions.
  41  */
  42 #define CTRLMMR_LOCK_KICK0                              0x01008
  43 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL                   0x68ef3490
  44 #define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK                BIT(0)
  45 #define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT               0
  46 #define CTRLMMR_LOCK_KICK1                              0x0100c
  47 #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL                   0xd172bc5a
  48
  49 /* MCU SCRATCHPAD usage */
  50 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START      CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
  51
  52 #endif /* __ASM_ARCH_J721E_HARDWARE_H */