arch/arm/mach-k3/am6_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AM6: SoC specific initialization
   4  *
   5  * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <init.h>
  11 #include <asm/io.h>
  12 #include <spl.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/sysfw-loader.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include "common.h"
  17 #include <dm.h>
  18 #include <dm/uclass-internal.h>
  19 #include <dm/pinctrl.h>
  20 #include <linux/soc/ti/ti_sci_protocol.h>
  21 #include <mmc.h>
  22
  23 #ifdef CONFIG_SPL_BUILD
  24 #ifdef CONFIG_K3_LOAD_SYSFW
  25 #ifdef CONFIG_TI_SECURE_DEVICE
  26 struct fwl_data main_cbass_fwls[] = {
  27         { "MMCSD1_CFG", 2057, 1 },
  28         { "MMCSD0_CFG", 2058, 1 },
  29         { "USB3SS0_SLV0", 2176, 2 },
  30         { "PCIE0_SLV", 2336, 8 },
  31         { "PCIE1_SLV", 2337, 8 },
  32         { "PCIE0_CFG", 2688, 1 },
  33         { "PCIE1_CFG", 2689, 1 },
  34 }, mcu_cbass_fwls[] = {
  35         { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
  36         { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
  37         { "MCU_FSS0_S1", 1033, 8 },
  38         { "MCU_FSS0_S0", 1036, 8 },
  39         { "MCU_CPSW0", 1220, 1 },
  40 };
  41 #endif
  42 #endif
  43
  44 static void mmr_unlock(u32 base, u32 partition)
  45 {
  46         /* Translate the base address */
  47         phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  48
  49         /* Unlock the requested partition if locked using two-step sequence */
  50         writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  51         writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  52 }
  53
  54 static void ctrl_mmr_unlock(void)
  55 {
  56         /* Unlock all WKUP_CTRL_MMR0 module registers */
  57         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  58         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  59         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  60         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  61         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  62         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  63
  64         /* Unlock all MCU_CTRL_MMR0 module registers */
  65         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  66         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  67         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  68         mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  69
  70         /* Unlock all CTRL_MMR0 module registers */
  71         mmr_unlock(CTRL_MMR0_BASE, 0);
  72         mmr_unlock(CTRL_MMR0_BASE, 1);
  73         mmr_unlock(CTRL_MMR0_BASE, 2);
  74         mmr_unlock(CTRL_MMR0_BASE, 3);
  75         mmr_unlock(CTRL_MMR0_BASE, 6);
  76         mmr_unlock(CTRL_MMR0_BASE, 7);
  77 }
  78
  79 /*
  80  * This uninitialized global variable would normal end up in the .bss section,
  81  * but the .bss is cleared between writing and reading this variable, so move
  82  * it to the .data section.
  83  */
  84 u32 bootindex __attribute__((section(".data")));
  85
  86 static void store_boot_index_from_rom(void)
  87 {
  88         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  89 }
  90
  91 #if defined(CONFIG_K3_LOAD_SYSFW)
  92 void k3_mmc_stop_clock(void)
  93 {
  94         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  95                 struct mmc *mmc = find_mmc_device(0);
  96
  97                 if (!mmc)
  98                         return;
  99
 100                 mmc->saved_clock = mmc->clock;
 101                 mmc_set_clock(mmc, 0, true);
 102         }
 103 }
 104
 105 void k3_mmc_restart_clock(void)
 106 {
 107         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 108                 struct mmc *mmc = find_mmc_device(0);
 109
 110                 if (!mmc)
 111                         return;
 112
 113                 mmc_set_clock(mmc, mmc->saved_clock, false);
 114         }
 115 }
 116 #endif
 117
 118 void board_init_f(ulong dummy)
 119 {
 120 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
 121         struct udevice *dev;
 122         int ret;
 123 #endif
 124         /*
 125          * Cannot delay this further as there is a chance that
 126          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
 127          */
 128         store_boot_index_from_rom();
 129
 130         /* Make all control module registers accessible */
 131         ctrl_mmr_unlock();
 132
 133 #ifdef CONFIG_CPU_V7R
 134         disable_linefill_optimization();
 135         setup_k3_mpu_regions();
 136 #endif
 137
 138         /* Init DM early in-order to invoke system controller */
 139         spl_early_init();
 140
 141 #ifdef CONFIG_K3_EARLY_CONS
 142         /*
 143          * Allow establishing an early console as required for example when
 144          * doing a UART-based boot. Note that this console may not "survive"
 145          * through a SYSFW PM-init step and will need a re-init in some way
 146          * due to changing module clock frequencies.
 147          */
 148         early_console_init();
 149 #endif
 150
 151 #ifdef CONFIG_K3_LOAD_SYSFW
 152         /*
 153          * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
 154          * regardless of the result of pinctrl. Do this without probing the
 155          * device, but instead by searching the device that would request the
 156          * given sequence number if probed. The UART will be used by the system
 157          * firmware (SYSFW) image for various purposes and SYSFW depends on us
 158          * to initialize its pin settings.
 159          */
 160         ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
 161         if (!ret)
 162                 pinctrl_select_state(dev, "default");
 163
 164         /*
 165          * Load, start up, and configure system controller firmware while
 166          * also populating the SYSFW post-PM configuration callback hook.
 167          */
 168         k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
 169
 170         /* Prepare console output */
 171         preloader_console_init();
 172
 173         /* Disable ROM configured firewalls right after loading sysfw */
 174 #ifdef CONFIG_TI_SECURE_DEVICE
 175         remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
 176         remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
 177 #endif
 178 #else
 179         /* Prepare console output */
 180         preloader_console_init();
 181 #endif
 182
 183         /* Output System Firmware version info */
 184         k3_sysfw_print_ver();
 185
 186         /* Perform EEPROM-based board detection */
 187         do_board_detect();
 188
 189 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
 190         ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
 191                                           &dev);
 192         if (ret)
 193                 printf("AVS init failed: %d\n", ret);
 194 #endif
 195
 196 #ifdef CONFIG_K3_AM654_DDRSS
 197         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 198         if (ret)
 199                 panic("DRAM init failed: %d\n", ret);
 200 #endif
 201         spl_enable_dcache();
 202 }
 203
 204 u32 spl_mmc_boot_mode(const u32 boot_device)
 205 {
 206 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
 207         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 208
 209         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 210                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 211
 212         /* eMMC boot0 mode is only supported for primary boot */
 213         if (bootindex == K3_PRIMARY_BOOTMODE &&
 214             bootmode == BOOT_DEVICE_MMC1)
 215                 return MMCSD_MODE_EMMCBOOT;
 216 #endif
 217
 218         /* Everything else use filesystem if available */
 219 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 220         return MMCSD_MODE_FS;
 221 #else
 222         return MMCSD_MODE_RAW;
 223 #endif
 224 }
 225
 226 static u32 __get_backup_bootmedia(u32 devstat)
 227 {
 228         u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 229                         CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 230
 231         switch (bkup_boot) {
 232         case BACKUP_BOOT_DEVICE_USB:
 233                 return BOOT_DEVICE_USB;
 234         case BACKUP_BOOT_DEVICE_UART:
 235                 return BOOT_DEVICE_UART;
 236         case BACKUP_BOOT_DEVICE_ETHERNET:
 237                 return BOOT_DEVICE_ETHERNET;
 238         case BACKUP_BOOT_DEVICE_MMC2:
 239         {
 240                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 241                             CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 242                 if (port == 0x0)
 243                         return BOOT_DEVICE_MMC1;
 244                 return BOOT_DEVICE_MMC2;
 245         }
 246         case BACKUP_BOOT_DEVICE_SPI:
 247                 return BOOT_DEVICE_SPI;
 248         case BACKUP_BOOT_DEVICE_HYPERFLASH:
 249                 return BOOT_DEVICE_HYPERFLASH;
 250         case BACKUP_BOOT_DEVICE_I2C:
 251                 return BOOT_DEVICE_I2C;
 252         };
 253
 254         return BOOT_DEVICE_RAM;
 255 }
 256
 257 static u32 __get_primary_bootmedia(u32 devstat)
 258 {
 259         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 260                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 261
 262         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 263                 bootmode = BOOT_DEVICE_SPI;
 264
 265         if (bootmode == BOOT_DEVICE_MMC2) {
 266                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
 267                             CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
 268                 if (port == 0x0)
 269                         bootmode = BOOT_DEVICE_MMC1;
 270         } else if (bootmode == BOOT_DEVICE_MMC1) {
 271                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
 272                             CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
 273                 if (port == 0x1)
 274                         bootmode = BOOT_DEVICE_MMC2;
 275         }
 276
 277         return bootmode;
 278 }
 279
 280 u32 spl_boot_device(void)
 281 {
 282         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 283
 284         if (bootindex == K3_PRIMARY_BOOTMODE)
 285                 return __get_primary_bootmedia(devstat);
 286         else
 287                 return __get_backup_bootmedia(devstat);
 288 }
 289 #endif
 290
 291 #ifdef CONFIG_SYS_K3_SPL_ATF
 292
 293 #define AM6_DEV_MCU_RTI0                        134
 294 #define AM6_DEV_MCU_RTI1                        135
 295 #define AM6_DEV_MCU_ARMSS0_CPU0                 159
 296 #define AM6_DEV_MCU_ARMSS0_CPU1                 245
 297
 298 void release_resources_for_core_shutdown(void)
 299 {
 300         struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 301         struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
 302         struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
 303         int ret;
 304         u32 i;
 305
 306         const u32 put_device_ids[] = {
 307                 AM6_DEV_MCU_RTI0,
 308                 AM6_DEV_MCU_RTI1,
 309         };
 310
 311         /* Iterate through list of devices to put (shutdown) */
 312         for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
 313                 u32 id = put_device_ids[i];
 314
 315                 ret = dev_ops->put_device(ti_sci, id);
 316                 if (ret)
 317                         panic("Failed to put device %u (%d)\n", id, ret);
 318         }
 319
 320         const u32 put_core_ids[] = {
 321                 AM6_DEV_MCU_ARMSS0_CPU1,
 322                 AM6_DEV_MCU_ARMSS0_CPU0,        /* Handle CPU0 after CPU1 */
 323         };
 324
 325         /* Iterate through list of cores to put (shutdown) */
 326         for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
 327                 u32 id = put_core_ids[i];
 328
 329                 /*
 330                  * Queue up the core shutdown request. Note that this call
 331                  * needs to be followed up by an actual invocation of an WFE
 332                  * or WFI CPU instruction.
 333                  */
 334                 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
 335                 if (ret)
 336                         panic("Failed sending core %u shutdown message (%d)\n",
 337                               id, ret);
 338         }
 339 }
 340 #endif