arch/arm/mach-imx/mx6/clock.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <div64.h>
   9 #include <log.h>
  10 #include <asm/io.h>
  11 #include <linux/errno.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 enum pll_clocks {
  18         PLL_SYS,        /* System PLL */
  19         PLL_BUS,        /* System Bus PLL*/
  20         PLL_USBOTG,     /* OTG USB PLL */
  21         PLL_ENET,       /* ENET PLL */
  22         PLL_AUDIO,      /* AUDIO PLL */
  23         PLL_VIDEO,      /* VIDEO PLL */
  24 };
  25
  26 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  27
  28 #ifdef CONFIG_MXC_OCOTP
  29 void enable_ocotp_clk(unsigned char enable)
  30 {
  31         u32 reg;
  32
  33         reg = __raw_readl(&imx_ccm->CCGR2);
  34         if (enable)
  35                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  36         else
  37                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  38         __raw_writel(reg, &imx_ccm->CCGR2);
  39 }
  40 #endif
  41
  42 #ifdef CONFIG_NAND_MXS
  43 void setup_gpmi_io_clk(u32 cfg)
  44 {
  45         /* Disable clocks per ERR007177 from MX6 errata */
  46         clrbits_le32(&imx_ccm->CCGR4,
  47                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  48                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  49                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  50                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  51                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  52
  53 #if defined(CONFIG_MX6SX)
  54         clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  55
  56         clrsetbits_le32(&imx_ccm->cs2cdr,
  57                         MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
  58                         MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
  59                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
  60                         cfg);
  61
  62         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  63 #else
  64         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  65
  66         clrsetbits_le32(&imx_ccm->cs2cdr,
  67                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  68                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  69                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  70                         cfg);
  71
  72         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  73 #endif
  74         setbits_le32(&imx_ccm->CCGR4,
  75                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  76                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  77                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  78                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  79                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  80 }
  81 #endif
  82
  83 void enable_usboh3_clk(unsigned char enable)
  84 {
  85         u32 reg;
  86
  87         reg = __raw_readl(&imx_ccm->CCGR6);
  88         if (enable)
  89                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  90         else
  91                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  92         __raw_writel(reg, &imx_ccm->CCGR6);
  93
  94 }
  95
  96 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
  97 void enable_enet_clk(unsigned char enable)
  98 {
  99         u32 mask, *addr;
 100
 101         if (is_mx6ull()) {
 102                 mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
 103                 addr = &imx_ccm->CCGR0;
 104         } else if (is_mx6ul()) {
 105                 mask = MXC_CCM_CCGR3_ENET_MASK;
 106                 addr = &imx_ccm->CCGR3;
 107         } else {
 108                 mask = MXC_CCM_CCGR1_ENET_MASK;
 109                 addr = &imx_ccm->CCGR1;
 110         }
 111
 112         if (enable)
 113                 setbits_le32(addr, mask);
 114         else
 115                 clrbits_le32(addr, mask);
 116 }
 117 #endif
 118
 119 #ifdef CONFIG_MXC_UART
 120 void enable_uart_clk(unsigned char enable)
 121 {
 122         u32 mask;
 123
 124         if (is_mx6ul() || is_mx6ull())
 125                 mask = MXC_CCM_CCGR5_UART_MASK;
 126         else
 127                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 128
 129         if (enable)
 130                 setbits_le32(&imx_ccm->CCGR5, mask);
 131         else
 132                 clrbits_le32(&imx_ccm->CCGR5, mask);
 133 }
 134 #endif
 135
 136 #ifdef CONFIG_MMC
 137 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 138 {
 139         u32 mask;
 140
 141         if (bus_num > 3)
 142                 return -EINVAL;
 143
 144         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 145         if (enable)
 146                 setbits_le32(&imx_ccm->CCGR6, mask);
 147         else
 148                 clrbits_le32(&imx_ccm->CCGR6, mask);
 149
 150         return 0;
 151 }
 152 #endif
 153
 154 #ifdef CONFIG_SYS_I2C_MXC
 155 /* i2c_num can be from 0 - 3 */
 156 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 157 {
 158         u32 reg;
 159         u32 mask;
 160         u32 *addr;
 161
 162         if (i2c_num > 3)
 163                 return -EINVAL;
 164         if (i2c_num < 3) {
 165                 mask = MXC_CCM_CCGR_CG_MASK
 166                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 167                         + (i2c_num << 1));
 168                 reg = __raw_readl(&imx_ccm->CCGR2);
 169                 if (enable)
 170                         reg |= mask;
 171                 else
 172                         reg &= ~mask;
 173                 __raw_writel(reg, &imx_ccm->CCGR2);
 174         } else {
 175                 if (is_mx6sll())
 176                         return -EINVAL;
 177                 if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
 178                         mask = MXC_CCM_CCGR6_I2C4_MASK;
 179                         addr = &imx_ccm->CCGR6;
 180                 } else {
 181                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
 182                         addr = &imx_ccm->CCGR1;
 183                 }
 184                 reg = __raw_readl(addr);
 185                 if (enable)
 186                         reg |= mask;
 187                 else
 188                         reg &= ~mask;
 189                 __raw_writel(reg, addr);
 190         }
 191         return 0;
 192 }
 193 #endif
 194
 195 /* spi_num can be from 0 - SPI_MAX_NUM */
 196 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 197 {
 198         u32 reg;
 199         u32 mask;
 200
 201         if (spi_num > SPI_MAX_NUM)
 202                 return -EINVAL;
 203
 204         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 205         reg = __raw_readl(&imx_ccm->CCGR1);
 206         if (enable)
 207                 reg |= mask;
 208         else
 209                 reg &= ~mask;
 210         __raw_writel(reg, &imx_ccm->CCGR1);
 211         return 0;
 212 }
 213 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 214 {
 215         u32 div, test_div, pll_num, pll_denom;
 216
 217         switch (pll) {
 218         case PLL_SYS:
 219                 div = __raw_readl(&imx_ccm->analog_pll_sys);
 220                 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
 221
 222                 return (infreq * div) >> 1;
 223         case PLL_BUS:
 224                 div = __raw_readl(&imx_ccm->analog_pll_528);
 225                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 226
 227                 return infreq * (20 + (div << 1));
 228         case PLL_USBOTG:
 229                 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
 230                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 231
 232                 return infreq * (20 + (div << 1));
 233         case PLL_ENET:
 234                 div = __raw_readl(&imx_ccm->analog_pll_enet);
 235                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 236
 237                 return 25000000 * (div + (div >> 1) + 1);
 238         case PLL_AUDIO:
 239                 div = __raw_readl(&imx_ccm->analog_pll_audio);
 240                 if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
 241                         return 0;
 242                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 243                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
 244                         return MXC_HCLK;
 245                 pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
 246                 pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
 247                 test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
 248                         BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
 249                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
 250                 if (test_div == 3) {
 251                         debug("Error test_div\n");
 252                         return 0;
 253                 }
 254                 test_div = 1 << (2 - test_div);
 255
 256                 return infreq * (div + pll_num / pll_denom) / test_div;
 257         case PLL_VIDEO:
 258                 div = __raw_readl(&imx_ccm->analog_pll_video);
 259                 if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
 260                         return 0;
 261                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 262                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
 263                         return MXC_HCLK;
 264                 pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
 265                 pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
 266                 test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
 267                         BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 268                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 269                 if (test_div == 3) {
 270                         debug("Error test_div\n");
 271                         return 0;
 272                 }
 273                 test_div = 1 << (2 - test_div);
 274
 275                 return infreq * (div + pll_num / pll_denom) / test_div;
 276         default:
 277                 return 0;
 278         }
 279         /* NOTREACHED */
 280 }
 281 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 282 {
 283         u32 div;
 284         u64 freq;
 285
 286         switch (pll) {
 287         case PLL_BUS:
 288                 if (!is_mx6ul() && !is_mx6ull()) {
 289                         if (pfd_num == 3) {
 290                                 /* No PFD3 on PLL2 */
 291                                 return 0;
 292                         }
 293                 }
 294                 div = __raw_readl(&imx_ccm->analog_pfd_528);
 295                 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
 296                 break;
 297         case PLL_USBOTG:
 298                 div = __raw_readl(&imx_ccm->analog_pfd_480);
 299                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 300                 break;
 301         default:
 302                 /* No PFD on other PLL                                       */
 303                 return 0;
 304         }
 305
 306         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 307                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 308 }
 309
 310 static u32 get_mcu_main_clk(void)
 311 {
 312         u32 reg, freq;
 313
 314         reg = __raw_readl(&imx_ccm->cacrr);
 315         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 316         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 317         freq = decode_pll(PLL_SYS, MXC_HCLK);
 318
 319         return freq / (reg + 1);
 320 }
 321
 322 u32 get_periph_clk(void)
 323 {
 324         u32 reg, div = 0, freq = 0;
 325
 326         reg = __raw_readl(&imx_ccm->cbcdr);
 327         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 328                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
 329                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 330                 reg = __raw_readl(&imx_ccm->cbcmr);
 331                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 332                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 333
 334                 switch (reg) {
 335                 case 0:
 336                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 337                         break;
 338                 case 1:
 339                 case 2:
 340                         freq = MXC_HCLK;
 341                         break;
 342                 default:
 343                         break;
 344                 }
 345         } else {
 346                 reg = __raw_readl(&imx_ccm->cbcmr);
 347                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 348                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 349
 350                 switch (reg) {
 351                 case 0:
 352                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 353                         break;
 354                 case 1:
 355                         freq = mxc_get_pll_pfd(PLL_BUS, 2);
 356                         break;
 357                 case 2:
 358                         freq = mxc_get_pll_pfd(PLL_BUS, 0);
 359                         break;
 360                 case 3:
 361                         /* static / 2 divider */
 362                         freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 363                         break;
 364                 default:
 365                         break;
 366                 }
 367         }
 368
 369         return freq / (div + 1);
 370 }
 371
 372 static u32 get_ipg_clk(void)
 373 {
 374         u32 reg, ipg_podf;
 375
 376         reg = __raw_readl(&imx_ccm->cbcdr);
 377         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 378         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 379
 380         return get_ahb_clk() / (ipg_podf + 1);
 381 }
 382
 383 static u32 get_ipg_per_clk(void)
 384 {
 385         u32 reg, perclk_podf;
 386
 387         reg = __raw_readl(&imx_ccm->cscmr1);
 388         if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
 389             is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
 390                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 391                         return MXC_HCLK; /* OSC 24Mhz */
 392         }
 393
 394         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 395
 396         return get_ipg_clk() / (perclk_podf + 1);
 397 }
 398
 399 static u32 get_uart_clk(void)
 400 {
 401         u32 reg, uart_podf;
 402         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 403         reg = __raw_readl(&imx_ccm->cscdr1);
 404
 405         if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
 406             is_mx6sll() || is_mx6ull()) {
 407                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 408                         freq = MXC_HCLK;
 409         }
 410
 411         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 412         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 413
 414         return freq / (uart_podf + 1);
 415 }
 416
 417 static u32 get_cspi_clk(void)
 418 {
 419         u32 reg, cspi_podf;
 420
 421         reg = __raw_readl(&imx_ccm->cscdr2);
 422         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 423                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 424
 425         if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
 426             is_mx6sll() || is_mx6ull()) {
 427                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 428                         return MXC_HCLK / (cspi_podf + 1);
 429         }
 430
 431         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 432 }
 433
 434 static u32 get_axi_clk(void)
 435 {
 436         u32 root_freq, axi_podf;
 437         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
 438
 439         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 440         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 441
 442         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 443                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 444                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 445                 else
 446                         root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 447         } else
 448                 root_freq = get_periph_clk();
 449
 450         return  root_freq / (axi_podf + 1);
 451 }
 452
 453 static u32 get_emi_slow_clk(void)
 454 {
 455         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 456
 457         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 458         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 459         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 460         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 461         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 462
 463         switch (emi_clk_sel) {
 464         case 0:
 465                 root_freq = get_axi_clk();
 466                 break;
 467         case 1:
 468                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 469                 break;
 470         case 2:
 471                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
 472                 break;
 473         case 3:
 474                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
 475                 break;
 476         }
 477
 478         return root_freq / (emi_slow_podf + 1);
 479 }
 480
 481 static u32 get_mmdc_ch0_clk(void)
 482 {
 483         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 484         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 485
 486         u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 487
 488         if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
 489             is_mx6sll()) {
 490                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 491                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 492                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 493                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 494                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
 495                         if (is_mx6sl()) {
 496                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 497                                         freq = MXC_HCLK;
 498                                 else
 499                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 500                         } else {
 501                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 502                                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 503                                 else
 504                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 505                         }
 506                 } else {
 507                         per2_clk2_podf = 0;
 508                         switch ((cbcmr &
 509                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 510                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 511                         case 0:
 512                                 freq = decode_pll(PLL_BUS, MXC_HCLK);
 513                                 break;
 514                         case 1:
 515                                 freq = mxc_get_pll_pfd(PLL_BUS, 2);
 516                                 break;
 517                         case 2:
 518                                 freq = mxc_get_pll_pfd(PLL_BUS, 0);
 519                                 break;
 520                         case 3:
 521                                 if (is_mx6sl()) {
 522                                         freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
 523                                         break;
 524                                 }
 525
 526                                 pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
 527                                 switch (pmu_misc2_audio_div) {
 528                                 case 0:
 529                                 case 2:
 530                                         pmu_misc2_audio_div = 1;
 531                                         break;
 532                                 case 1:
 533                                         pmu_misc2_audio_div = 2;
 534                                         break;
 535                                 case 3:
 536                                         pmu_misc2_audio_div = 4;
 537                                         break;
 538                                 }
 539                                 freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
 540                                         pmu_misc2_audio_div;
 541                                 break;
 542                         }
 543                 }
 544                 return freq / (podf + 1) / (per2_clk2_podf + 1);
 545         } else {
 546                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 547                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 548                 return get_periph_clk() / (podf + 1);
 549         }
 550 }
 551
 552 #if defined(CONFIG_VIDEO_MXS)
 553 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
 554                             u32 post_div)
 555 {
 556         u32 reg = 0;
 557         ulong start;
 558
 559         debug("pll5 div = %d, num = %d, denom = %d\n",
 560               pll_div, pll_num, pll_denom);
 561
 562         /* Power up PLL5 video */
 563         writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
 564                BM_ANADIG_PLL_VIDEO_BYPASS |
 565                BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 566                BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 567                &imx_ccm->analog_pll_video_clr);
 568
 569         /* Set div, num and denom */
 570         switch (post_div) {
 571         case 1:
 572                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 573                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
 574                        &imx_ccm->analog_pll_video_set);
 575                 break;
 576         case 2:
 577                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 578                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
 579                        &imx_ccm->analog_pll_video_set);
 580                 break;
 581         case 4:
 582                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 583                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
 584                        &imx_ccm->analog_pll_video_set);
 585                 break;
 586         default:
 587                 puts("Wrong test_div!\n");
 588                 return -EINVAL;
 589         }
 590
 591         writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
 592                &imx_ccm->analog_pll_video_num);
 593         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
 594                &imx_ccm->analog_pll_video_denom);
 595
 596         /* Wait PLL5 lock */
 597         start = get_timer(0);   /* Get current timestamp */
 598
 599         do {
 600                 reg = readl(&imx_ccm->analog_pll_video);
 601                 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
 602                         /* Enable PLL out */
 603                         writel(BM_ANADIG_PLL_VIDEO_ENABLE,
 604                                &imx_ccm->analog_pll_video_set);
 605                         return 0;
 606                 }
 607         } while (get_timer(0) < (start + 10)); /* Wait 10ms */
 608
 609         puts("Lock PLL5 timeout\n");
 610
 611         return -ETIME;
 612 }
 613
 614 /*
 615  * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
 616  *
 617  * 'freq' using KHz as unit, see driver/video/mxsfb.c.
 618  */
 619 void mxs_set_lcdclk(u32 base_addr, u32 freq)
 620 {
 621         u32 reg = 0;
 622         u32 hck = MXC_HCLK / 1000;
 623         /* DIV_SELECT ranges from 27 to 54 */
 624         u32 min = hck * 27;
 625         u32 max = hck * 54;
 626         u32 temp, best = 0;
 627         u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
 628         u32 pll_div, pll_num, pll_denom, post_div = 1;
 629
 630         debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 631
 632         if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
 633             !is_mx6sll()) {
 634                 debug("This chip not support lcd!\n");
 635                 return;
 636         }
 637
 638         if (!is_mx6sl()) {
 639                 if (base_addr == LCDIF1_BASE_ADDR) {
 640                         reg = readl(&imx_ccm->cscdr2);
 641                         /* Can't change clocks when clock not from pre-mux */
 642                         if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
 643                                 return;
 644                 }
 645         }
 646
 647         if (is_mx6sx()) {
 648                 reg = readl(&imx_ccm->cscdr2);
 649                 /* Can't change clocks when clock not from pre-mux */
 650                 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
 651                         return;
 652         }
 653
 654         temp = freq * max_pred * max_postd;
 655         if (temp < min) {
 656                 /*
 657                  * Register: PLL_VIDEO
 658                  * Bit Field: POST_DIV_SELECT
 659                  * 00 — Divide by 4.
 660                  * 01 — Divide by 2.
 661                  * 10 — Divide by 1.
 662                  * 11 — Reserved
 663                  * No need to check post_div(1)
 664                  */
 665                 for (post_div = 2; post_div <= 4; post_div <<= 1) {
 666                         if ((temp * post_div) > min) {
 667                                 freq *= post_div;
 668                                 break;
 669                         }
 670                 }
 671
 672                 if (post_div > 4) {
 673                         printf("Fail to set rate to %dkhz", freq);
 674                         return;
 675                 }
 676         }
 677
 678         /* Choose the best pred and postd to match freq for lcd */
 679         for (i = 1; i <= max_pred; i++) {
 680                 for (j = 1; j <= max_postd; j++) {
 681                         temp = freq * i * j;
 682                         if (temp > max || temp < min)
 683                                 continue;
 684                         if (best == 0 || temp < best) {
 685                                 best = temp;
 686                                 pred = i;
 687                                 postd = j;
 688                         }
 689                 }
 690         }
 691
 692         if (best == 0) {
 693                 printf("Fail to set rate to %dKHz", freq);
 694                 return;
 695         }
 696
 697         debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
 698
 699         pll_div = best / hck;
 700         pll_denom = 1000000;
 701         pll_num = (best - hck * pll_div) * pll_denom / hck;
 702
 703         /*
 704          *                                  pll_num
 705          *             (24MHz * (pll_div + --------- ))
 706          *                                 pll_denom
 707          *freq KHz =  --------------------------------
 708          *             post_div * pred * postd * 1000
 709          */
 710
 711         if (base_addr == LCDIF1_BASE_ADDR) {
 712                 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 713                         return;
 714
 715                 enable_lcdif_clock(base_addr, 0);
 716                 if (!is_mx6sl()) {
 717                         /* Select pre-lcd clock to PLL5 and set pre divider */
 718                         clrsetbits_le32(&imx_ccm->cscdr2,
 719                                         MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
 720                                         MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
 721                                         (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
 722                                         ((pred - 1) <<
 723                                          MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
 724
 725                         /* Set the post divider */
 726                         clrsetbits_le32(&imx_ccm->cbcmr,
 727                                         MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
 728                                         ((postd - 1) <<
 729                                         MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
 730                 } else {
 731                         /* Select pre-lcd clock to PLL5 and set pre divider */
 732                         clrsetbits_le32(&imx_ccm->cscdr2,
 733                                         MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
 734                                         MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
 735                                         (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
 736                                         ((pred - 1) <<
 737                                          MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
 738
 739                         /* Set the post divider */
 740                         clrsetbits_le32(&imx_ccm->cscmr1,
 741                                         MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
 742                                         (((postd - 1)^0x6) <<
 743                                          MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
 744                 }
 745
 746                 enable_lcdif_clock(base_addr, 1);
 747         } else if (is_mx6sx()) {
 748                 /* Setting LCDIF2 for i.MX6SX */
 749                 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 750                         return;
 751
 752                 enable_lcdif_clock(base_addr, 0);
 753                 /* Select pre-lcd clock to PLL5 and set pre divider */
 754                 clrsetbits_le32(&imx_ccm->cscdr2,
 755                                 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
 756                                 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
 757                                 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
 758                                 ((pred - 1) <<
 759                                  MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
 760
 761                 /* Set the post divider */
 762                 clrsetbits_le32(&imx_ccm->cscmr1,
 763                                 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
 764                                 ((postd - 1) <<
 765                                  MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
 766
 767                 enable_lcdif_clock(base_addr, 1);
 768         }
 769 }
 770
 771 int enable_lcdif_clock(u32 base_addr, bool enable)
 772 {
 773         u32 reg = 0;
 774         u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
 775
 776         if (is_mx6sx()) {
 777                 if ((base_addr != LCDIF1_BASE_ADDR) &&
 778                     (base_addr != LCDIF2_BASE_ADDR)) {
 779                         puts("Wrong LCD interface!\n");
 780                         return -EINVAL;
 781                 }
 782                 /* Set to pre-mux clock at default */
 783                 lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
 784                         MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
 785                         MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
 786                 lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
 787                         (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
 788                          MXC_CCM_CCGR3_DISP_AXI_MASK) :
 789                         (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
 790                          MXC_CCM_CCGR3_DISP_AXI_MASK);
 791         } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
 792                 if (base_addr != LCDIF1_BASE_ADDR) {
 793                         puts("Wrong LCD interface!\n");
 794                         return -EINVAL;
 795                 }
 796                 /* Set to pre-mux clock at default */
 797                 lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
 798                 lcdif_ccgr3_mask =  MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
 799         } else if (is_mx6sl()) {
 800                 if (base_addr != LCDIF1_BASE_ADDR) {
 801                         puts("Wrong LCD interface!\n");
 802                         return -EINVAL;
 803                 }
 804
 805                 reg = readl(&imx_ccm->CCGR3);
 806                 reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
 807                          MXC_CCM_CCGR3_LCDIF_PIX_MASK);
 808                 writel(reg, &imx_ccm->CCGR3);
 809
 810                 if (enable) {
 811                         reg = readl(&imx_ccm->cscdr3);
 812                         reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
 813                         reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
 814                         writel(reg, &imx_ccm->cscdr3);
 815
 816                         reg = readl(&imx_ccm->CCGR3);
 817                         reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
 818                                 MXC_CCM_CCGR3_LCDIF_PIX_MASK;
 819                         writel(reg, &imx_ccm->CCGR3);
 820                 }
 821
 822                 return 0;
 823         } else {
 824                 return 0;
 825         }
 826
 827         /* Gate LCDIF clock first */
 828         reg = readl(&imx_ccm->CCGR3);
 829         reg &= ~lcdif_ccgr3_mask;
 830         writel(reg, &imx_ccm->CCGR3);
 831
 832         reg = readl(&imx_ccm->CCGR2);
 833         reg &= ~MXC_CCM_CCGR2_LCD_MASK;
 834         writel(reg, &imx_ccm->CCGR2);
 835
 836         if (enable) {
 837                 /* Select pre-mux */
 838                 reg = readl(&imx_ccm->cscdr2);
 839                 reg &= ~lcdif_clk_sel_mask;
 840                 writel(reg, &imx_ccm->cscdr2);
 841
 842                 /* Enable the LCDIF pix clock */
 843                 reg = readl(&imx_ccm->CCGR3);
 844                 reg |= lcdif_ccgr3_mask;
 845                 writel(reg, &imx_ccm->CCGR3);
 846
 847                 reg = readl(&imx_ccm->CCGR2);
 848                 reg |= MXC_CCM_CCGR2_LCD_MASK;
 849                 writel(reg, &imx_ccm->CCGR2);
 850         }
 851
 852         return 0;
 853 }
 854 #endif
 855
 856 #ifdef CONFIG_FSL_QSPI
 857 /* qspi_num can be from 0 - 1 */
 858 void enable_qspi_clk(int qspi_num)
 859 {
 860         u32 reg = 0;
 861         /* Enable QuadSPI clock */
 862         switch (qspi_num) {
 863         case 0:
 864                 /* disable the clock gate */
 865                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 866
 867                 /* set 50M  : (50 = 396 / 2 / 4) */
 868                 reg = readl(&imx_ccm->cscmr1);
 869                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 870                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 871                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 872                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 873                 writel(reg, &imx_ccm->cscmr1);
 874
 875                 /* enable the clock gate */
 876                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 877                 break;
 878         case 1:
 879                 /*
 880                  * disable the clock gate
 881                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 882                  * disable both of them.
 883                  */
 884                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 885                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 886
 887                 /* set 50M  : (50 = 396 / 2 / 4) */
 888                 reg = readl(&imx_ccm->cs2cdr);
 889                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 890                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 891                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 892                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 893                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 894                 writel(reg, &imx_ccm->cs2cdr);
 895
 896                 /*enable the clock gate*/
 897                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 898                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 899                 break;
 900         default:
 901                 break;
 902         }
 903 }
 904 #endif
 905
 906 #ifdef CONFIG_FEC_MXC
 907 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 908 {
 909         u32 reg = 0;
 910         s32 timeout = 100000;
 911
 912         struct anatop_regs __iomem *anatop =
 913                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 914
 915         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 916                 return -EINVAL;
 917
 918         reg = readl(&anatop->pll_enet);
 919
 920         if (fec_id == 0) {
 921                 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 922                 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
 923         } else if (fec_id == 1) {
 924                 /* Only i.MX6SX/UL support ENET2 */
 925                 if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
 926                         return -EINVAL;
 927                 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
 928                 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
 929         } else {
 930                 return -EINVAL;
 931         }
 932
 933         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 934             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 935                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 936                 writel(reg, &anatop->pll_enet);
 937                 while (timeout--) {
 938                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 939                                 break;
 940                 }
 941                 if (timeout < 0)
 942                         return -ETIMEDOUT;
 943         }
 944
 945         /* Enable FEC clock */
 946         if (fec_id == 0)
 947                 reg |= BM_ANADIG_PLL_ENET_ENABLE;
 948         else
 949                 reg |= BM_ANADIG_PLL_ENET2_ENABLE;
 950         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 951         writel(reg, &anatop->pll_enet);
 952
 953 #ifdef CONFIG_MX6SX
 954         /* Disable enet system clcok before switching clock parent */
 955         reg = readl(&imx_ccm->CCGR3);
 956         reg &= ~MXC_CCM_CCGR3_ENET_MASK;
 957         writel(reg, &imx_ccm->CCGR3);
 958
 959         /*
 960          * Set enet ahb clock to 200MHz
 961          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 962          */
 963         reg = readl(&imx_ccm->chsccdr);
 964         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 965                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 966                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 967         /* PLL2 PFD2 */
 968         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 969         /* Div = 2*/
 970         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 971         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 972         writel(reg, &imx_ccm->chsccdr);
 973
 974         /* Enable enet system clock */
 975         reg = readl(&imx_ccm->CCGR3);
 976         reg |= MXC_CCM_CCGR3_ENET_MASK;
 977         writel(reg, &imx_ccm->CCGR3);
 978 #endif
 979         return 0;
 980 }
 981 #endif
 982
 983 static u32 get_usdhc_clk(u32 port)
 984 {
 985         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 986         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 987         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 988
 989         if (is_mx6ul() || is_mx6ull()) {
 990                 if (port > 1)
 991                         return 0;
 992         }
 993
 994         if (is_mx6sll()) {
 995                 if (port > 2)
 996                         return 0;
 997         }
 998
 999         switch (port) {
1000         case 0:
1001                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
1002                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
1003                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
1004
1005                 break;
1006         case 1:
1007                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
1008                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
1009                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
1010
1011                 break;
1012         case 2:
1013                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
1014                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
1015                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
1016
1017                 break;
1018         case 3:
1019                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
1020                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
1021                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
1022
1023                 break;
1024         default:
1025                 break;
1026         }
1027
1028         if (clk_sel)
1029                 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
1030         else
1031                 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
1032
1033         return root_freq / (usdhc_podf + 1);
1034 }
1035
1036 u32 imx_get_uartclk(void)
1037 {
1038         return get_uart_clk();
1039 }
1040
1041 u32 imx_get_fecclk(void)
1042 {
1043         return mxc_get_clock(MXC_IPG_CLK);
1044 }
1045
1046 #if defined(CONFIG_SATA) || defined(CONFIG_PCIE_IMX)
1047 static int enable_enet_pll(uint32_t en)
1048 {
1049         struct mxc_ccm_reg *const imx_ccm
1050                 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
1051         s32 timeout = 100000;
1052         u32 reg = 0;
1053
1054         /* Enable PLLs */
1055         reg = readl(&imx_ccm->analog_pll_enet);
1056         reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
1057         writel(reg, &imx_ccm->analog_pll_enet);
1058         reg |= BM_ANADIG_PLL_SYS_ENABLE;
1059         while (timeout--) {
1060                 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
1061                         break;
1062         }
1063         if (timeout <= 0)
1064                 return -EIO;
1065         reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
1066         writel(reg, &imx_ccm->analog_pll_enet);
1067         reg |= en;
1068         writel(reg, &imx_ccm->analog_pll_enet);
1069         return 0;
1070 }
1071 #endif
1072
1073 #ifdef CONFIG_SATA
1074 static void ungate_sata_clock(void)
1075 {
1076         struct mxc_ccm_reg *const imx_ccm =
1077                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1078
1079         /* Enable SATA clock. */
1080         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1081 }
1082
1083 int enable_sata_clock(void)
1084 {
1085         ungate_sata_clock();
1086         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
1087 }
1088
1089 void disable_sata_clock(void)
1090 {
1091         struct mxc_ccm_reg *const imx_ccm =
1092                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1093
1094         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1095 }
1096 #endif
1097
1098 #ifdef CONFIG_PCIE_IMX
1099 static void ungate_pcie_clock(void)
1100 {
1101         struct mxc_ccm_reg *const imx_ccm =
1102                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1103
1104         /* Enable PCIe clock. */
1105         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
1106 }
1107
1108 int enable_pcie_clock(void)
1109 {
1110         struct anatop_regs *anatop_regs =
1111                 (struct anatop_regs *)ANATOP_BASE_ADDR;
1112         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1113         u32 lvds1_clk_sel;
1114
1115         /*
1116          * Here be dragons!
1117          *
1118          * The register ANATOP_MISC1 is not documented in the Freescale
1119          * MX6RM. The register that is mapped in the ANATOP space and
1120          * marked as ANATOP_MISC1 is actually documented in the PMU section
1121          * of the datasheet as PMU_MISC1.
1122          *
1123          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1124          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1125          * for PCI express link that is clocked from the i.MX6.
1126          */
1127 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
1128 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
1129 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
1130 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1131 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1132
1133         if (is_mx6sx())
1134                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
1135         else
1136                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1137
1138         clrsetbits_le32(&anatop_regs->ana_misc1,
1139                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1140                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1141                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1142
1143         /* PCIe reference clock sourced from AXI. */
1144         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1145
1146         /* Party time! Ungate the clock to the PCIe. */
1147 #ifdef CONFIG_SATA
1148         ungate_sata_clock();
1149 #endif
1150         ungate_pcie_clock();
1151
1152         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1153                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1154 }
1155 #endif
1156
1157 #ifdef CONFIG_IMX_HAB
1158 void hab_caam_clock_enable(unsigned char enable)
1159 {
1160         u32 reg;
1161
1162         if (is_mx6ull() || is_mx6sll()) {
1163                 /* CG5, DCP clock */
1164                 reg = __raw_readl(&imx_ccm->CCGR0);
1165                 if (enable)
1166                         reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
1167                 else
1168                         reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
1169                 __raw_writel(reg, &imx_ccm->CCGR0);
1170         } else {
1171                 /* CG4 ~ CG6, CAAM clocks */
1172                 reg = __raw_readl(&imx_ccm->CCGR0);
1173                 if (enable)
1174                         reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1175                                 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1176                                 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1177                 else
1178                         reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1179                                 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1180                                 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1181                 __raw_writel(reg, &imx_ccm->CCGR0);
1182         }
1183
1184         /* EMI slow clk */
1185         reg = __raw_readl(&imx_ccm->CCGR6);
1186         if (enable)
1187                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1188         else
1189                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1190         __raw_writel(reg, &imx_ccm->CCGR6);
1191 }
1192 #endif
1193
1194 static void enable_pll3(void)
1195 {
1196         struct anatop_regs __iomem *anatop =
1197                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1198
1199         /* make sure pll3 is enabled */
1200         if ((readl(&anatop->usb1_pll_480_ctrl) &
1201                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1202                 /* enable pll's power */
1203                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1204                        &anatop->usb1_pll_480_ctrl_set);
1205                 writel(0x80, &anatop->ana_misc2_clr);
1206                 /* wait for pll lock */
1207                 while ((readl(&anatop->usb1_pll_480_ctrl) &
1208                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1209                         ;
1210                 /* disable bypass */
1211                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1212                        &anatop->usb1_pll_480_ctrl_clr);
1213                 /* enable pll output */
1214                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1215                        &anatop->usb1_pll_480_ctrl_set);
1216         }
1217 }
1218
1219 void enable_thermal_clk(void)
1220 {
1221         enable_pll3();
1222 }
1223
1224 #ifdef CONFIG_MTD_NOR_FLASH
1225 void enable_eim_clk(unsigned char enable)
1226 {
1227         u32 reg;
1228
1229         reg = __raw_readl(&imx_ccm->CCGR6);
1230         if (enable)
1231                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1232         else
1233                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1234         __raw_writel(reg, &imx_ccm->CCGR6);
1235 }
1236 #endif
1237
1238 unsigned int mxc_get_clock(enum mxc_clock clk)
1239 {
1240         switch (clk) {
1241         case MXC_ARM_CLK:
1242                 return get_mcu_main_clk();
1243         case MXC_PER_CLK:
1244                 return get_periph_clk();
1245         case MXC_AHB_CLK:
1246                 return get_ahb_clk();
1247         case MXC_IPG_CLK:
1248                 return get_ipg_clk();
1249         case MXC_IPG_PERCLK:
1250         case MXC_I2C_CLK:
1251                 return get_ipg_per_clk();
1252         case MXC_UART_CLK:
1253                 return get_uart_clk();
1254         case MXC_CSPI_CLK:
1255                 return get_cspi_clk();
1256         case MXC_AXI_CLK:
1257                 return get_axi_clk();
1258         case MXC_EMI_SLOW_CLK:
1259                 return get_emi_slow_clk();
1260         case MXC_DDR_CLK:
1261                 return get_mmdc_ch0_clk();
1262         case MXC_ESDHC_CLK:
1263                 return get_usdhc_clk(0);
1264         case MXC_ESDHC2_CLK:
1265                 return get_usdhc_clk(1);
1266         case MXC_ESDHC3_CLK:
1267                 return get_usdhc_clk(2);
1268         case MXC_ESDHC4_CLK:
1269                 return get_usdhc_clk(3);
1270         case MXC_SATA_CLK:
1271                 return get_ahb_clk();
1272         default:
1273                 printf("Unsupported MXC CLK: %d\n", clk);
1274                 break;
1275         }
1276
1277         return 0;
1278 }
1279
1280 #ifndef CONFIG_MX6SX
1281 void enable_ipu_clock(void)
1282 {
1283         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1284
1285         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
1286
1287         if (is_mx6dqp()) {
1288                 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1289                 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1290         }
1291 }
1292
1293 void disable_ipu_clock(void)
1294 {
1295         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1296
1297         clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
1298
1299         if (is_mx6dqp()) {
1300                 clrbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1301                 clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1302         }
1303 }
1304 #endif
1305
1306 #ifndef CONFIG_SPL_BUILD
1307 /*
1308  * Dump some core clockes.
1309  */
1310 int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
1311                       char *const argv[])
1312 {
1313         u32 freq;
1314         freq = decode_pll(PLL_SYS, MXC_HCLK);
1315         printf("PLL_SYS    %8d MHz\n", freq / 1000000);
1316         freq = decode_pll(PLL_BUS, MXC_HCLK);
1317         printf("PLL_BUS    %8d MHz\n", freq / 1000000);
1318         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1319         printf("PLL_OTG    %8d MHz\n", freq / 1000000);
1320         freq = decode_pll(PLL_ENET, MXC_HCLK);
1321         printf("PLL_NET    %8d MHz\n", freq / 1000000);
1322
1323         printf("\n");
1324         printf("ARM        %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
1325         printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1326         printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1327 #ifdef CONFIG_MXC_SPI
1328         printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1329 #endif
1330         printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1331         printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1332         printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1333         printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1334         printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1335         printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1336         printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
1337         printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
1338         printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
1339
1340         return 0;
1341 }
1342
1343 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
1344         defined(CONFIG_MX6S)
1345 static void disable_ldb_di_clock_sources(void)
1346 {
1347         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1348         int reg;
1349
1350         /* Make sure PFDs are disabled at boot. */
1351         reg = readl(&mxc_ccm->analog_pfd_528);
1352         /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
1353         if (is_mx6sdl())
1354                 reg |= 0x80008080;
1355         else
1356                 reg |= 0x80808080;
1357         writel(reg, &mxc_ccm->analog_pfd_528);
1358
1359         /* Disable PLL3 PFDs */
1360         reg = readl(&mxc_ccm->analog_pfd_480);
1361         reg |= 0x80808080;
1362         writel(reg, &mxc_ccm->analog_pfd_480);
1363
1364         /* Disable PLL5 */
1365         reg = readl(&mxc_ccm->analog_pll_video);
1366         reg &= ~(1 << 13);
1367         writel(reg, &mxc_ccm->analog_pll_video);
1368 }
1369
1370 static void enable_ldb_di_clock_sources(void)
1371 {
1372         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1373         int reg;
1374
1375         reg = readl(&mxc_ccm->analog_pfd_528);
1376         if (is_mx6sdl())
1377                 reg &= ~(0x80008080);
1378         else
1379                 reg &= ~(0x80808080);
1380         writel(reg, &mxc_ccm->analog_pfd_528);
1381
1382         reg = readl(&mxc_ccm->analog_pfd_480);
1383         reg &= ~(0x80808080);
1384         writel(reg, &mxc_ccm->analog_pfd_480);
1385 }
1386
1387 /*
1388  * Try call this function as early in the boot process as possible since the
1389  * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
1390  */
1391 void select_ldb_di_clock_source(enum ldb_di_clock clk)
1392 {
1393         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1394         int reg;
1395
1396         /*
1397          * Need to follow a strict procedure when changing the LDB
1398          * clock, else we can introduce a glitch. Things to keep in
1399          * mind:
1400          * 1. The current and new parent clocks must be disabled.
1401          * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
1402          * no CG bit.
1403          * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
1404          * the top four options are in one mux and the PLL3 option along
1405          * with another option is in the second mux. There is third mux
1406          * used to decide between the first and second mux.
1407          * The code below switches the parent to the bottom mux first
1408          * and then manipulates the top mux. This ensures that no glitch
1409          * will enter the divider.
1410          *
1411          * Need to disable MMDC_CH1 clock manually as there is no CG bit
1412          * for this clock. The only way to disable this clock is to move
1413          * it to pll3_sw_clk and then to disable pll3_sw_clk
1414          * Make sure periph2_clk2_sel is set to pll3_sw_clk
1415          */
1416
1417         /* Disable all ldb_di clock parents */
1418         disable_ldb_di_clock_sources();
1419
1420         /* Set MMDC_CH1 mask bit */
1421         reg = readl(&mxc_ccm->ccdr);
1422         reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1423         writel(reg, &mxc_ccm->ccdr);
1424
1425         /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
1426         reg = readl(&mxc_ccm->cbcmr);
1427         reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
1428         writel(reg, &mxc_ccm->cbcmr);
1429
1430         /*
1431          * Set the periph2_clk_sel to the top mux so that
1432          * mmdc_ch1 is from pll3_sw_clk.
1433          */
1434         reg = readl(&mxc_ccm->cbcdr);
1435         reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1436         writel(reg, &mxc_ccm->cbcdr);
1437
1438         /* Wait for the clock switch */
1439         while (readl(&mxc_ccm->cdhipr))
1440                 ;
1441         /* Disable pll3_sw_clk by selecting bypass clock source */
1442         reg = readl(&mxc_ccm->ccsr);
1443         reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1444         writel(reg, &mxc_ccm->ccsr);
1445
1446         /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
1447         reg = readl(&mxc_ccm->cs2cdr);
1448         reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1449               | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1450         writel(reg, &mxc_ccm->cs2cdr);
1451
1452         /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
1453         reg = readl(&mxc_ccm->cs2cdr);
1454         reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1455               | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1456         reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1457               | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1458         writel(reg, &mxc_ccm->cs2cdr);
1459
1460         /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
1461         reg = readl(&mxc_ccm->cs2cdr);
1462         reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1463               | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1464         reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1465               | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1466         writel(reg, &mxc_ccm->cs2cdr);
1467
1468         /* Unbypass pll3_sw_clk */
1469         reg = readl(&mxc_ccm->ccsr);
1470         reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1471         writel(reg, &mxc_ccm->ccsr);
1472
1473         /*
1474          * Set the periph2_clk_sel back to the bottom mux so that
1475          * mmdc_ch1 is from its original parent.
1476          */
1477         reg = readl(&mxc_ccm->cbcdr);
1478         reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1479         writel(reg, &mxc_ccm->cbcdr);
1480
1481         /* Wait for the clock switch */
1482         while (readl(&mxc_ccm->cdhipr))
1483                 ;
1484         /* Clear MMDC_CH1 mask bit */
1485         reg = readl(&mxc_ccm->ccdr);
1486         reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1487         writel(reg, &mxc_ccm->ccdr);
1488
1489         enable_ldb_di_clock_sources();
1490 }
1491 #endif
1492
1493 /***************************************************/
1494
1495 U_BOOT_CMD(
1496         clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
1497         "display clocks",
1498         ""
1499 );
1500 #endif