1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/cache.h>
16 #include <linux/errno.h>
18 #include <asm/mach-imx/boot_mode.h>
20 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
21 #error "CPU_TYPE not defined"
27 int system_rev = 0x51000;
29 int system_rev = 0x53000;
31 int reg = __raw_readl(ROM_SI_REV);
33 #if defined(CONFIG_MX51)
36 system_rev |= CHIP_REV_1_1;
39 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
40 system_rev |= CHIP_REV_2_5;
42 system_rev |= CHIP_REV_2_0;
45 system_rev |= CHIP_REV_3_0;
48 system_rev |= CHIP_REV_1_0;
53 system_rev |= CHIP_REV_1_0;
60 #ifdef CONFIG_REVISION_TAG
61 u32 __weak get_board_rev(void)
67 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
68 void enable_caches(void)
70 /* Enable D-cache. I-cache is already enabled in start.S */
75 #if defined(CONFIG_FEC_MXC)
76 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
79 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
80 struct fuse_bank *bank = &iim->bank[1];
81 struct fuse_bank1_regs *fuse =
82 (struct fuse_bank1_regs *)bank->fuse_regs;
84 for (i = 0; i < 6; i++)
85 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
90 void boot_mode_apply(unsigned cfg_val)
92 writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
95 * cfg_val will be used for
96 * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
98 * If bit 28 of LPGR is set upon watchdog reset,
99 * bits[25:0] of LPGR will move to SBMR.
101 const struct boot_mode soc_boot_modes[] = {
102 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
103 /* usb or serial download */
104 {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
105 {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
106 {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
107 {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
108 {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
109 {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
110 /* 4 bit bus width */
111 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
112 {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
113 {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
114 {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},