arch/arm/mach-imx/imx8m/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2019 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/mach-imx/hab.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/syscounter.h>
  19 #include <asm/armv8/mmu.h>
  20 #include <dm/uclass.h>
  21 #include <errno.h>
  22 #include <fdt_support.h>
  23 #include <fsl_wdog.h>
  24 #include <imx_sip.h>
  25 #include <linux/bitops.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #if defined(CONFIG_IMX_HAB)
  30 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  31         .bank = 1,
  32         .word = 3,
  33 };
  34 #endif
  35
  36 int timer_init(void)
  37 {
  38 #ifdef CONFIG_SPL_BUILD
  39         struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  40         unsigned long freq = readl(&sctr->cntfid0);
  41
  42         /* Update with accurate clock frequency */
  43         asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  44
  45         clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  46                         SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  47 #endif
  48
  49         gd->arch.tbl = 0;
  50         gd->arch.tbu = 0;
  51
  52         return 0;
  53 }
  54
  55 void enable_tzc380(void)
  56 {
  57         struct iomuxc_gpr_base_regs *gpr =
  58                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  59
  60         /* Enable TZASC and lock setting */
  61         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  62         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  63         if (is_imx8mm() || is_imx8mn() || is_imx8mp())
  64                 setbits_le32(&gpr->gpr[10], BIT(1));
  65         /*
  66          * set Region 0 attribute to allow secure and non-secure
  67          * read/write permission. Found some masters like usb dwc3
  68          * controllers can't work with secure memory.
  69          */
  70         writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  71 }
  72
  73 void set_wdog_reset(struct wdog_regs *wdog)
  74 {
  75         /*
  76          * Output WDOG_B signal to reset external pmic or POR_B decided by
  77          * the board design. Without external reset, the peripherals/DDR/
  78          * PMIC are not reset, that may cause system working abnormal.
  79          * WDZST bit is write-once only bit. Align this bit in kernel,
  80          * otherwise kernel code will have no chance to set this bit.
  81          */
  82         setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  83 }
  84
  85 static struct mm_region imx8m_mem_map[] = {
  86         {
  87                 /* ROM */
  88                 .virt = 0x0UL,
  89                 .phys = 0x0UL,
  90                 .size = 0x100000UL,
  91                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  92                          PTE_BLOCK_OUTER_SHARE
  93         }, {
  94                 /* CAAM */
  95                 .virt = 0x100000UL,
  96                 .phys = 0x100000UL,
  97                 .size = 0x8000UL,
  98                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  99                          PTE_BLOCK_NON_SHARE |
 100                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 101         }, {
 102                 /* TCM */
 103                 .virt = 0x7C0000UL,
 104                 .phys = 0x7C0000UL,
 105                 .size = 0x80000UL,
 106                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 107                          PTE_BLOCK_NON_SHARE |
 108                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 109         }, {
 110                 /* OCRAM */
 111                 .virt = 0x900000UL,
 112                 .phys = 0x900000UL,
 113                 .size = 0x200000UL,
 114                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 115                          PTE_BLOCK_OUTER_SHARE
 116         }, {
 117                 /* AIPS */
 118                 .virt = 0xB00000UL,
 119                 .phys = 0xB00000UL,
 120                 .size = 0x3f500000UL,
 121                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 122                          PTE_BLOCK_NON_SHARE |
 123                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 124         }, {
 125                 /* DRAM1 */
 126                 .virt = 0x40000000UL,
 127                 .phys = 0x40000000UL,
 128                 .size = PHYS_SDRAM_SIZE,
 129                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 130                          PTE_BLOCK_OUTER_SHARE
 131 #ifdef PHYS_SDRAM_2_SIZE
 132         }, {
 133                 /* DRAM2 */
 134                 .virt = 0x100000000UL,
 135                 .phys = 0x100000000UL,
 136                 .size = PHYS_SDRAM_2_SIZE,
 137                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 138                          PTE_BLOCK_OUTER_SHARE
 139 #endif
 140         }, {
 141                 /* List terminator */
 142                 0,
 143         }
 144 };
 145
 146 struct mm_region *mem_map = imx8m_mem_map;
 147
 148 void enable_caches(void)
 149 {
 150         /*
 151          * If OPTEE runs, remove OPTEE memory from MMU table to
 152          * avoid speculative prefetch. OPTEE runs at the top of
 153          * the first memory bank
 154          */
 155         if (rom_pointer[1])
 156                 imx8m_mem_map[5].size -= rom_pointer[1];
 157
 158         icache_enable();
 159         dcache_enable();
 160 }
 161
 162 static u32 get_cpu_variant_type(u32 type)
 163 {
 164         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 165         struct fuse_bank *bank = &ocotp->bank[1];
 166         struct fuse_bank1_regs *fuse =
 167                 (struct fuse_bank1_regs *)bank->fuse_regs;
 168
 169         u32 value = readl(&fuse->tester4);
 170
 171         if (type == MXC_CPU_IMX8MQ) {
 172                 if ((value & 0x3) == 0x2)
 173                         return MXC_CPU_IMX8MD;
 174                 else if (value & 0x200000)
 175                         return MXC_CPU_IMX8MQL;
 176
 177         } else if (type == MXC_CPU_IMX8MM) {
 178                 switch (value & 0x3) {
 179                 case 2:
 180                         if (value & 0x1c0000)
 181                                 return MXC_CPU_IMX8MMDL;
 182                         else
 183                                 return MXC_CPU_IMX8MMD;
 184                 case 3:
 185                         if (value & 0x1c0000)
 186                                 return MXC_CPU_IMX8MMSL;
 187                         else
 188                                 return MXC_CPU_IMX8MMS;
 189                 default:
 190                         if (value & 0x1c0000)
 191                                 return MXC_CPU_IMX8MML;
 192                         break;
 193                 }
 194         } else if (type == MXC_CPU_IMX8MN) {
 195                 switch (value & 0x3) {
 196                 case 2:
 197                         if (value & 0x1000000)
 198                                 return MXC_CPU_IMX8MNDL;
 199                         else
 200                                 return MXC_CPU_IMX8MND;
 201                 case 3:
 202                         if (value & 0x1000000)
 203                                 return MXC_CPU_IMX8MNSL;
 204                         else
 205                                 return MXC_CPU_IMX8MNS;
 206                 default:
 207                         if (value & 0x1000000)
 208                                 return MXC_CPU_IMX8MNL;
 209                         break;
 210                 }
 211         }
 212
 213         return type;
 214 }
 215
 216 u32 get_cpu_rev(void)
 217 {
 218         struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 219         u32 reg = readl(&ana_pll->digprog);
 220         u32 type = (reg >> 16) & 0xff;
 221         u32 major_low = (reg >> 8) & 0xff;
 222         u32 rom_version;
 223
 224         reg &= 0xff;
 225
 226         /* iMX8MP */
 227         if (major_low == 0x43) {
 228                 return (MXC_CPU_IMX8MP << 12) | reg;
 229         } else if (major_low == 0x42) {
 230                 /* iMX8MN */
 231                 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
 232         } else if (major_low == 0x41) {
 233                 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
 234         } else {
 235                 if (reg == CHIP_REV_1_0) {
 236                         /*
 237                          * For B0 chip, the DIGPROG is not updated,
 238                          * it is still TO1.0. we have to check ROM
 239                          * version or OCOTP_READ_FUSE_DATA.
 240                          * 0xff0055aa is magic number for B1.
 241                          */
 242                         if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
 243                                 reg = CHIP_REV_2_1;
 244                         } else {
 245                                 rom_version =
 246                                         readl((void __iomem *)ROM_VERSION_A0);
 247                                 if (rom_version != CHIP_REV_1_0) {
 248                                         rom_version = readl((void __iomem *)ROM_VERSION_B0);
 249                                         rom_version &= 0xff;
 250                                         if (rom_version == CHIP_REV_2_0)
 251                                                 reg = CHIP_REV_2_0;
 252                                 }
 253                         }
 254                 }
 255
 256                 type = get_cpu_variant_type(type);
 257         }
 258
 259         return (type << 12) | reg;
 260 }
 261
 262 static void imx_set_wdog_powerdown(bool enable)
 263 {
 264         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 265         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 266         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 267
 268         /* Write to the PDE (Power Down Enable) bit */
 269         writew(enable, &wdog1->wmcr);
 270         writew(enable, &wdog2->wmcr);
 271         writew(enable, &wdog3->wmcr);
 272 }
 273
 274 int arch_cpu_init_dm(void)
 275 {
 276         struct udevice *dev;
 277         int ret;
 278
 279         if (CONFIG_IS_ENABLED(CLK)) {
 280                 ret = uclass_get_device_by_name(UCLASS_CLK,
 281                                                 "clock-controller@30380000",
 282                                                 &dev);
 283                 if (ret < 0) {
 284                         printf("Failed to find clock node. Check device tree\n");
 285                         return ret;
 286                 }
 287         }
 288
 289         return 0;
 290 }
 291
 292 int arch_cpu_init(void)
 293 {
 294         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 295         /*
 296          * ROM might disable clock for SCTR,
 297          * enable the clock before timer_init.
 298          */
 299         if (IS_ENABLED(CONFIG_SPL_BUILD))
 300                 clock_enable(CCGR_SCTR, 1);
 301         /*
 302          * Init timer at very early state, because sscg pll setting
 303          * will use it
 304          */
 305         timer_init();
 306
 307         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 308                 clock_init();
 309                 imx_set_wdog_powerdown(false);
 310         }
 311
 312         if (is_imx8mq()) {
 313                 clock_enable(CCGR_OCOTP, 1);
 314                 if (readl(&ocotp->ctrl) & 0x200)
 315                         writel(0x200, &ocotp->ctrl_clr);
 316         }
 317
 318         return 0;
 319 }
 320
 321 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
 322 struct rom_api *g_rom_api = (struct rom_api *)0x980;
 323
 324 enum boot_device get_boot_device(void)
 325 {
 326         volatile gd_t *pgd = gd;
 327         int ret;
 328         u32 boot;
 329         u16 boot_type;
 330         u8 boot_instance;
 331         enum boot_device boot_dev = SD1_BOOT;
 332
 333         ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
 334                                           ((uintptr_t)&boot) ^ QUERY_BT_DEV);
 335         gd = pgd;
 336
 337         if (ret != ROM_API_OKAY) {
 338                 puts("ROMAPI: failure at query_boot_info\n");
 339                 return -1;
 340         }
 341
 342         boot_type = boot >> 16;
 343         boot_instance = (boot >> 8) & 0xff;
 344
 345         switch (boot_type) {
 346         case BT_DEV_TYPE_SD:
 347                 boot_dev = boot_instance + SD1_BOOT;
 348                 break;
 349         case BT_DEV_TYPE_MMC:
 350                 boot_dev = boot_instance + MMC1_BOOT;
 351                 break;
 352         case BT_DEV_TYPE_NAND:
 353                 boot_dev = NAND_BOOT;
 354                 break;
 355         case BT_DEV_TYPE_FLEXSPINOR:
 356                 boot_dev = QSPI_BOOT;
 357                 break;
 358         case BT_DEV_TYPE_USB:
 359                 boot_dev = USB_BOOT;
 360                 break;
 361         default:
 362                 break;
 363         }
 364
 365         return boot_dev;
 366 }
 367 #endif
 368
 369 bool is_usb_boot(void)
 370 {
 371         return get_boot_device() == USB_BOOT;
 372 }
 373
 374 #ifdef CONFIG_OF_SYSTEM_SETUP
 375 int ft_system_setup(void *blob, bd_t *bd)
 376 {
 377         int i = 0;
 378         int rc;
 379         int nodeoff;
 380
 381         /* Disable the CPU idle for A0 chip since the HW does not support it */
 382         if (is_soc_rev(CHIP_REV_1_0)) {
 383                 static const char * const nodes_path[] = {
 384                         "/cpus/cpu@0",
 385                         "/cpus/cpu@1",
 386                         "/cpus/cpu@2",
 387                         "/cpus/cpu@3",
 388                 };
 389
 390                 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
 391                         nodeoff = fdt_path_offset(blob, nodes_path[i]);
 392                         if (nodeoff < 0)
 393                                 continue; /* Not found, skip it */
 394
 395                         debug("Found %s node\n", nodes_path[i]);
 396
 397                         rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
 398                         if (rc == -FDT_ERR_NOTFOUND)
 399                                 continue;
 400                         if (rc) {
 401                                 printf("Unable to update property %s:%s, err=%s\n",
 402                                        nodes_path[i], "status", fdt_strerror(rc));
 403                                 return rc;
 404                         }
 405
 406                         debug("Remove %s:%s\n", nodes_path[i],
 407                                "cpu-idle-states");
 408                 }
 409         }
 410
 411         return 0;
 412 }
 413 #endif
 414
 415 #if !CONFIG_IS_ENABLED(SYSRESET)
 416 void reset_cpu(ulong addr)
 417 {
 418         struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 419
 420         /* Clear WDA to trigger WDOG_B immediately */
 421         writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
 422
 423         while (1) {
 424                 /*
 425                  * spin for .5 seconds before reset
 426                  */
 427         }
 428 }
 429 #endif
 430
 431 #if defined(CONFIG_ARCH_MISC_INIT)
 432 static void acquire_buildinfo(void)
 433 {
 434         u64 atf_commit = 0;
 435
 436         /* Get ARM Trusted Firmware commit id */
 437         atf_commit = call_imx_sip(IMX_SIP_BUILDINFO,
 438                                   IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
 439         if (atf_commit == 0xffffffff) {
 440                 debug("ATF does not support build info\n");
 441                 atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
 442         }
 443
 444         printf("\n BuildInfo:\n  - ATF %s\n\n", (char *)&atf_commit);
 445 }
 446
 447 int arch_misc_init(void)
 448 {
 449         acquire_buildinfo();
 450
 451         return 0;
 452 }
 453 #endif
 454
 455 void imx_tmu_arch_init(void *reg_base)
 456 {
 457         if (is_imx8mm() || is_imx8mn()) {
 458                 /* Load TCALIV and TASR from fuses */
 459                 struct ocotp_regs *ocotp =
 460                         (struct ocotp_regs *)OCOTP_BASE_ADDR;
 461                 struct fuse_bank *bank = &ocotp->bank[3];
 462                 struct fuse_bank3_regs *fuse =
 463                         (struct fuse_bank3_regs *)bank->fuse_regs;
 464
 465                 u32 tca_rt, tca_hr, tca_en;
 466                 u32 buf_vref, buf_slope;
 467
 468                 tca_rt = fuse->ana0 & 0xFF;
 469                 tca_hr = (fuse->ana0 & 0xFF00) >> 8;
 470                 tca_en = (fuse->ana0 & 0x2000000) >> 25;
 471
 472                 buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
 473                 buf_slope = (fuse->ana0 & 0xF0000) >> 16;
 474
 475                 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
 476                 writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
 477                        (ulong)reg_base + 0x30);
 478         }
 479 #ifdef CONFIG_IMX8MP
 480         /* Load TCALIV0/1/m40 and TRIM from fuses */
 481         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 482         struct fuse_bank *bank = &ocotp->bank[38];
 483         struct fuse_bank38_regs *fuse =
 484                 (struct fuse_bank38_regs *)bank->fuse_regs;
 485         struct fuse_bank *bank2 = &ocotp->bank[39];
 486         struct fuse_bank39_regs *fuse2 =
 487                 (struct fuse_bank39_regs *)bank2->fuse_regs;
 488         u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
 489         u32 reg;
 490         u32 tca40[2], tca25[2], tca105[2];
 491
 492         /* For blank sample */
 493         if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
 494             !fuse->ana_trim4 && !fuse2->ana_trim5) {
 495                 /* Use a default 25C binary codes */
 496                 tca25[0] = 1596;
 497                 tca25[1] = 1596;
 498                 writel(tca25[0], (ulong)reg_base + 0x30);
 499                 writel(tca25[1], (ulong)reg_base + 0x34);
 500                 return;
 501         }
 502
 503         buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
 504         buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
 505         bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
 506         bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
 507         vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
 508         writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
 509
 510         reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
 511         writel(reg, (ulong)reg_base + 0x3c);
 512
 513         tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
 514         tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
 515         tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
 516         tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
 517         tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
 518         tca25[1] = fuse2->ana_trim5 & 0xFFF;
 519         tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
 520
 521         /* use 25c for 1p calibration */
 522         writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
 523         writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
 524         writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
 525 #endif
 526 }