arch/arm/mach-imx/imx8m/clock_imx8mq.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <errno.h>
  15 #include <linux/delay.h>
  16 #include <linux/iopoll.h>
  17
  18 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  19
  20 static u32 get_root_clk(enum clk_root_index clock_id);
  21
  22 static u32 decode_frac_pll(enum clk_root_src frac_pll)
  23 {
  24         u32 pll_cfg0, pll_cfg1, pllout;
  25         u32 pll_refclk_sel, pll_refclk;
  26         u32 divr_val, divq_val, divf_val, divff, divfi;
  27         u32 pllout_div_shift, pllout_div_mask, pllout_div;
  28
  29         switch (frac_pll) {
  30         case ARM_PLL_CLK:
  31                 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
  32                 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
  33                 pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
  34                 pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
  35                 break;
  36         default:
  37                 printf("Frac PLL %d not supporte\n", frac_pll);
  38                 return 0;
  39         }
  40
  41         pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
  42         pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
  43
  44         /* Power down */
  45         if (pll_cfg0 & FRAC_PLL_PD_MASK)
  46                 return 0;
  47
  48         /* output not enabled */
  49         if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
  50                 return 0;
  51
  52         pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
  53
  54         if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
  55                 pll_refclk = 25000000u;
  56         else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
  57                 pll_refclk = 27000000u;
  58         else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
  59                 pll_refclk = 27000000u;
  60         else
  61                 pll_refclk = 0;
  62
  63         if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
  64                 return pll_refclk;
  65
  66         divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
  67                 FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
  68         divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
  69
  70         divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
  71                 FRAC_PLL_FRAC_DIV_CTL_SHIFT;
  72         divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
  73
  74         divf_val = 1 + divfi + divff / (1 << 24);
  75
  76         pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
  77                 ((divq_val + 1) * 2);
  78
  79         return pllout / (pllout_div + 1);
  80 }
  81
  82 static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
  83 {
  84         u32 pll_cfg0, pll_cfg1, pll_cfg2;
  85         u32 pll_refclk_sel, pll_refclk;
  86         u32 divr1, divr2, divf1, divf2, divq, div;
  87         u32 sse;
  88         u32 pll_clke;
  89         u32 pllout_div_shift, pllout_div_mask, pllout_div;
  90         u32 pllout;
  91
  92         switch (sscg_pll) {
  93         case SYSTEM_PLL1_800M_CLK:
  94         case SYSTEM_PLL1_400M_CLK:
  95         case SYSTEM_PLL1_266M_CLK:
  96         case SYSTEM_PLL1_200M_CLK:
  97         case SYSTEM_PLL1_160M_CLK:
  98         case SYSTEM_PLL1_133M_CLK:
  99         case SYSTEM_PLL1_100M_CLK:
 100         case SYSTEM_PLL1_80M_CLK:
 101         case SYSTEM_PLL1_40M_CLK:
 102                 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
 103                 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
 104                 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
 105                 pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
 106                 pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
 107                 break;
 108         case SYSTEM_PLL2_1000M_CLK:
 109         case SYSTEM_PLL2_500M_CLK:
 110         case SYSTEM_PLL2_333M_CLK:
 111         case SYSTEM_PLL2_250M_CLK:
 112         case SYSTEM_PLL2_200M_CLK:
 113         case SYSTEM_PLL2_166M_CLK:
 114         case SYSTEM_PLL2_125M_CLK:
 115         case SYSTEM_PLL2_100M_CLK:
 116         case SYSTEM_PLL2_50M_CLK:
 117                 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
 118                 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
 119                 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
 120                 pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
 121                 pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
 122                 break;
 123         case SYSTEM_PLL3_CLK:
 124                 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
 125                 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
 126                 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
 127                 pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
 128                 pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
 129                 break;
 130         case DRAM_PLL1_CLK:
 131                 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
 132                 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
 133                 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
 134                 pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
 135                 pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
 136                 break;
 137         default:
 138                 printf("sscg pll %d not supporte\n", sscg_pll);
 139                 return 0;
 140         }
 141
 142         switch (sscg_pll) {
 143         case DRAM_PLL1_CLK:
 144                 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
 145                 div = 1;
 146                 break;
 147         case SYSTEM_PLL3_CLK:
 148                 pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
 149                 div = 1;
 150                 break;
 151         case SYSTEM_PLL2_1000M_CLK:
 152         case SYSTEM_PLL1_800M_CLK:
 153                 pll_clke = SSCG_PLL_CLKE_MASK;
 154                 div = 1;
 155                 break;
 156         case SYSTEM_PLL2_500M_CLK:
 157         case SYSTEM_PLL1_400M_CLK:
 158                 pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
 159                 div = 2;
 160                 break;
 161         case SYSTEM_PLL2_333M_CLK:
 162         case SYSTEM_PLL1_266M_CLK:
 163                 pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
 164                 div = 3;
 165                 break;
 166         case SYSTEM_PLL2_250M_CLK:
 167         case SYSTEM_PLL1_200M_CLK:
 168                 pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
 169                 div = 4;
 170                 break;
 171         case SYSTEM_PLL2_200M_CLK:
 172         case SYSTEM_PLL1_160M_CLK:
 173                 pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
 174                 div = 5;
 175                 break;
 176         case SYSTEM_PLL2_166M_CLK:
 177         case SYSTEM_PLL1_133M_CLK:
 178                 pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
 179                 div = 6;
 180                 break;
 181         case SYSTEM_PLL2_125M_CLK:
 182         case SYSTEM_PLL1_100M_CLK:
 183                 pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
 184                 div = 8;
 185                 break;
 186         case SYSTEM_PLL2_100M_CLK:
 187         case SYSTEM_PLL1_80M_CLK:
 188                 pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
 189                 div = 10;
 190                 break;
 191         case SYSTEM_PLL2_50M_CLK:
 192         case SYSTEM_PLL1_40M_CLK:
 193                 pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
 194                 div = 20;
 195                 break;
 196         default:
 197                 printf("sscg pll %d not supporte\n", sscg_pll);
 198                 return 0;
 199         }
 200
 201         /* Power down */
 202         if (pll_cfg0 & SSCG_PLL_PD_MASK)
 203                 return 0;
 204
 205         /* output not enabled */
 206         if ((pll_cfg0 & pll_clke) == 0)
 207                 return 0;
 208
 209         pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
 210         pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
 211
 212         pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
 213
 214         if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
 215                 pll_refclk = 25000000u;
 216         else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
 217                 pll_refclk = 27000000u;
 218         else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
 219                 pll_refclk = 27000000u;
 220         else
 221                 pll_refclk = 0;
 222
 223         /* We assume bypass1/2 are the same value */
 224         if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
 225             (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
 226                 return pll_refclk;
 227
 228         divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
 229                 SSCG_PLL_REF_DIVR1_SHIFT;
 230         divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
 231                 SSCG_PLL_REF_DIVR2_SHIFT;
 232         divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
 233                 SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
 234         divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
 235                 SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
 236         divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
 237                 SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
 238         sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
 239
 240         if (sse)
 241                 sse = 8;
 242         else
 243                 sse = 2;
 244
 245         pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
 246                 (divr2 + 1) * (divf2 + 1) / (divq + 1);
 247
 248         return pllout / (pllout_div + 1) / div;
 249 }
 250
 251 static u32 get_root_src_clk(enum clk_root_src root_src)
 252 {
 253         switch (root_src) {
 254         case OSC_25M_CLK:
 255                 return 25000000;
 256         case OSC_27M_CLK:
 257                 return 27000000;
 258         case OSC_32K_CLK:
 259                 return 32768;
 260         case ARM_PLL_CLK:
 261                 return decode_frac_pll(root_src);
 262         case SYSTEM_PLL1_800M_CLK:
 263         case SYSTEM_PLL1_400M_CLK:
 264         case SYSTEM_PLL1_266M_CLK:
 265         case SYSTEM_PLL1_200M_CLK:
 266         case SYSTEM_PLL1_160M_CLK:
 267         case SYSTEM_PLL1_133M_CLK:
 268         case SYSTEM_PLL1_100M_CLK:
 269         case SYSTEM_PLL1_80M_CLK:
 270         case SYSTEM_PLL1_40M_CLK:
 271         case SYSTEM_PLL2_1000M_CLK:
 272         case SYSTEM_PLL2_500M_CLK:
 273         case SYSTEM_PLL2_333M_CLK:
 274         case SYSTEM_PLL2_250M_CLK:
 275         case SYSTEM_PLL2_200M_CLK:
 276         case SYSTEM_PLL2_166M_CLK:
 277         case SYSTEM_PLL2_125M_CLK:
 278         case SYSTEM_PLL2_100M_CLK:
 279         case SYSTEM_PLL2_50M_CLK:
 280         case SYSTEM_PLL3_CLK:
 281                 return decode_sscg_pll(root_src);
 282         case ARM_A53_ALT_CLK:
 283                 return get_root_clk(ARM_A53_CLK_ROOT);
 284         default:
 285                 return 0;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static u32 get_root_clk(enum clk_root_index clock_id)
 292 {
 293         enum clk_root_src root_src;
 294         u32 post_podf, pre_podf, root_src_clk;
 295
 296         if (clock_root_enabled(clock_id) <= 0)
 297                 return 0;
 298
 299         if (clock_get_prediv(clock_id, &pre_podf) < 0)
 300                 return 0;
 301
 302         if (clock_get_postdiv(clock_id, &post_podf) < 0)
 303                 return 0;
 304
 305         if (clock_get_src(clock_id, &root_src) < 0)
 306                 return 0;
 307
 308         root_src_clk = get_root_src_clk(root_src);
 309
 310         return root_src_clk / (post_podf + 1) / (pre_podf + 1);
 311 }
 312
 313 #ifdef CONFIG_MXC_OCOTP
 314 void enable_ocotp_clk(unsigned char enable)
 315 {
 316         clock_enable(CCGR_OCOTP, !!enable);
 317 }
 318 #endif
 319
 320 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
 321 {
 322         /* 0 - 3 is valid i2c num */
 323         if (i2c_num > 3)
 324                 return -EINVAL;
 325
 326         clock_enable(CCGR_I2C1 + i2c_num, !!enable);
 327
 328         return 0;
 329 }
 330
 331 u32 get_arm_core_clk(void)
 332 {
 333         enum clk_root_src root_src;
 334         u32 root_src_clk;
 335
 336         if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
 337                 return 0;
 338
 339         root_src_clk = get_root_src_clk(root_src);
 340
 341         return root_src_clk;
 342 }
 343
 344 unsigned int mxc_get_clock(enum mxc_clock clk)
 345 {
 346         u32 val;
 347
 348         switch (clk) {
 349         case MXC_ARM_CLK:
 350                 return get_arm_core_clk();
 351         case MXC_IPG_CLK:
 352                 clock_get_target_val(IPG_CLK_ROOT, &val);
 353                 val = val & 0x3;
 354                 return get_root_clk(AHB_CLK_ROOT) / (val + 1);
 355         case MXC_ESDHC_CLK:
 356                 return get_root_clk(USDHC1_CLK_ROOT);
 357         case MXC_ESDHC2_CLK:
 358                 return get_root_clk(USDHC2_CLK_ROOT);
 359         default:
 360                 return get_root_clk(clk);
 361         }
 362 }
 363
 364 u32 imx_get_uartclk(void)
 365 {
 366         return mxc_get_clock(UART1_CLK_ROOT);
 367 }
 368
 369 void mxs_set_lcdclk(u32 base_addr, u32 freq)
 370 {
 371         /*
 372          * LCDIF_PIXEL_CLK: select 800MHz root clock,
 373          * select pre divider 8, output is 100 MHz
 374          */
 375         clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
 376                              CLK_ROOT_SOURCE_SEL(4) |
 377                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
 378 }
 379
 380 void init_wdog_clk(void)
 381 {
 382         clock_enable(CCGR_WDOG1, 0);
 383         clock_enable(CCGR_WDOG2, 0);
 384         clock_enable(CCGR_WDOG3, 0);
 385         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 386                              CLK_ROOT_SOURCE_SEL(0));
 387         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 388                              CLK_ROOT_SOURCE_SEL(0));
 389         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 390                              CLK_ROOT_SOURCE_SEL(0));
 391         clock_enable(CCGR_WDOG1, 1);
 392         clock_enable(CCGR_WDOG2, 1);
 393         clock_enable(CCGR_WDOG3, 1);
 394 }
 395
 396
 397 void init_nand_clk(void)
 398 {
 399         clock_enable(CCGR_RAWNAND, 0);
 400         clock_set_target_val(NAND_CLK_ROOT,
 401                              CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
 402                              CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4));
 403         clock_enable(CCGR_RAWNAND, 1);
 404 }
 405
 406 void init_uart_clk(u32 index)
 407 {
 408         /* Set uart clock root 25M OSC */
 409         switch (index) {
 410         case 0:
 411                 clock_enable(CCGR_UART1, 0);
 412                 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
 413                                      CLK_ROOT_SOURCE_SEL(0));
 414                 clock_enable(CCGR_UART1, 1);
 415                 return;
 416         case 1:
 417                 clock_enable(CCGR_UART2, 0);
 418                 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
 419                                      CLK_ROOT_SOURCE_SEL(0));
 420                 clock_enable(CCGR_UART2, 1);
 421                 return;
 422         case 2:
 423                 clock_enable(CCGR_UART3, 0);
 424                 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
 425                                      CLK_ROOT_SOURCE_SEL(0));
 426                 clock_enable(CCGR_UART3, 1);
 427                 return;
 428         case 3:
 429                 clock_enable(CCGR_UART4, 0);
 430                 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
 431                                      CLK_ROOT_SOURCE_SEL(0));
 432                 clock_enable(CCGR_UART4, 1);
 433                 return;
 434         default:
 435                 printf("Invalid uart index\n");
 436                 return;
 437         }
 438 }
 439
 440 void init_clk_usdhc(u32 index)
 441 {
 442         /*
 443          * set usdhc clock root
 444          * sys pll1 400M
 445          */
 446         switch (index) {
 447         case 0:
 448                 clock_enable(CCGR_USDHC1, 0);
 449                 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
 450                                      CLK_ROOT_SOURCE_SEL(1));
 451                 clock_enable(CCGR_USDHC1, 1);
 452                 return;
 453         case 1:
 454                 clock_enable(CCGR_USDHC2, 0);
 455                 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
 456                                      CLK_ROOT_SOURCE_SEL(1));
 457                 clock_enable(CCGR_USDHC2, 1);
 458                 return;
 459         default:
 460                 printf("Invalid usdhc index\n");
 461                 return;
 462         }
 463 }
 464
 465 int set_clk_qspi(void)
 466 {
 467         /*
 468          * set qspi root
 469          * sys pll1 100M
 470          */
 471         clock_enable(CCGR_QSPI, 0);
 472         clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
 473                              CLK_ROOT_SOURCE_SEL(7));
 474         clock_enable(CCGR_QSPI, 1);
 475
 476         return 0;
 477 }
 478
 479 #ifdef CONFIG_FEC_MXC
 480 int set_clk_enet(enum enet_freq type)
 481 {
 482         u32 target;
 483         u32 enet1_ref;
 484
 485         switch (type) {
 486         case ENET_125MHZ:
 487                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
 488                 break;
 489         case ENET_50MHZ:
 490                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
 491                 break;
 492         case ENET_25MHZ:
 493                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
 494                 break;
 495         default:
 496                 return -EINVAL;
 497         }
 498
 499         /* disable the clock first */
 500         clock_enable(CCGR_ENET1, 0);
 501         clock_enable(CCGR_SIM_ENET, 0);
 502
 503         /* set enet axi clock 266Mhz */
 504         target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
 505                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 506                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 507         clock_set_target_val(ENET_AXI_CLK_ROOT, target);
 508
 509         target = CLK_ROOT_ON | enet1_ref |
 510                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 511                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 512         clock_set_target_val(ENET_REF_CLK_ROOT, target);
 513
 514         target = CLK_ROOT_ON |
 515                 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
 516                 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 517                 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 518         clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
 519
 520         /* enable clock */
 521         clock_enable(CCGR_SIM_ENET, 1);
 522         clock_enable(CCGR_ENET1, 1);
 523
 524         return 0;
 525 }
 526 #endif
 527
 528 u32 imx_get_fecclk(void)
 529 {
 530         return get_root_clk(ENET_AXI_CLK_ROOT);
 531 }
 532
 533 static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
 534         DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
 535                                 CLK_ROOT_PRE_DIV2),
 536         DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
 537                                 CLK_ROOT_PRE_DIV2),
 538         DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
 539                                 CLK_ROOT_PRE_DIV2),
 540 };
 541
 542 void dram_enable_bypass(ulong clk_val)
 543 {
 544         int i;
 545         struct dram_bypass_clk_setting *config;
 546
 547         for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
 548                 if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
 549                         break;
 550         }
 551
 552         if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
 553                 printf("No matched freq table %lu\n", clk_val);
 554                 return;
 555         }
 556
 557         config = &imx8mq_dram_bypass_tbl[i];
 558
 559         clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
 560                              CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
 561                              CLK_ROOT_PRE_DIV(config->alt_pre_div));
 562         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 563                              CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
 564                              CLK_ROOT_PRE_DIV(config->apb_pre_div));
 565         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 566                              CLK_ROOT_SOURCE_SEL(1));
 567 }
 568
 569 void dram_disable_bypass(void)
 570 {
 571         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 572                              CLK_ROOT_SOURCE_SEL(0));
 573         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 574                              CLK_ROOT_SOURCE_SEL(4) |
 575                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
 576 }
 577
 578 #ifdef CONFIG_SPL_BUILD
 579 void dram_pll_init(ulong pll_val)
 580 {
 581         u32 val;
 582         void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
 583         void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
 584
 585         /* Bypass */
 586         setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
 587         setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
 588
 589         switch (pll_val) {
 590         case MHZ(800):
 591                 val = readl(pll_cfg_reg2);
 592                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 593                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 594                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 595                          SSCG_PLL_REF_DIVR2_MASK);
 596                 val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
 597                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
 598                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
 599                 val |= SSCG_PLL_REF_DIVR2_VAL(29);
 600                 writel(val, pll_cfg_reg2);
 601                 break;
 602         case MHZ(600):
 603                 val = readl(pll_cfg_reg2);
 604                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 605                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 606                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 607                          SSCG_PLL_REF_DIVR2_MASK);
 608                 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
 609                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
 610                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
 611                 val |= SSCG_PLL_REF_DIVR2_VAL(29);
 612                 writel(val, pll_cfg_reg2);
 613                 break;
 614         case MHZ(400):
 615                 val = readl(pll_cfg_reg2);
 616                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 617                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 618                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 619                          SSCG_PLL_REF_DIVR2_MASK);
 620                 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
 621                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
 622                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
 623                 val |= SSCG_PLL_REF_DIVR2_VAL(29);
 624                 writel(val, pll_cfg_reg2);
 625                 break;
 626         case MHZ(167):
 627                 val = readl(pll_cfg_reg2);
 628                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 629                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 630                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 631                          SSCG_PLL_REF_DIVR2_MASK);
 632                 val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
 633                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
 634                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
 635                 val |= SSCG_PLL_REF_DIVR2_VAL(30);
 636                 writel(val, pll_cfg_reg2);
 637                 break;
 638         default:
 639                 break;
 640         }
 641
 642         /* Clear power down bit */
 643         clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
 644         /* Eanble ARM_PLL/SYS_PLL  */
 645         setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
 646
 647         /* Clear bypass */
 648         clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
 649         __udelay(100);
 650         clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
 651         /* Wait lock */
 652         while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
 653                 ;
 654 }
 655
 656 static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
 657 {
 658         void __iomem *pll_cfg0, __iomem *pll_cfg1;
 659         u32 val_cfg0, val_cfg1, divq;
 660         int ret;
 661
 662         switch (pll) {
 663         case ANATOP_ARM_PLL:
 664                 pll_cfg0 = &ana_pll->arm_pll_cfg0;
 665                 pll_cfg1 = &ana_pll->arm_pll_cfg1;
 666
 667                 if (val == FRAC_PLL_OUT_1000M) {
 668                         val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
 669                         divq = 0;
 670                 } else {
 671                         val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
 672                         divq = 1;
 673                 }
 674                 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
 675                         FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
 676                         FRAC_PLL_REFCLK_DIV_VAL(4) |
 677                         FRAC_PLL_OUTPUT_DIV_VAL(divq);
 678                 break;
 679         default:
 680                 return -EINVAL;
 681         }
 682
 683         /* bypass the clock */
 684         setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
 685         /* Set the value */
 686         writel(val_cfg1, pll_cfg1);
 687         writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
 688         val_cfg0 = readl(pll_cfg0);
 689         /* unbypass the clock */
 690         clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
 691         ret = readl_poll_timeout(pll_cfg0, val_cfg0,
 692                                  val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
 693         if (ret)
 694                 printf("%s timeout\n", __func__);
 695         clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
 696
 697         return 0;
 698 }
 699
 700
 701 int clock_init(void)
 702 {
 703         u32 grade;
 704
 705         clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
 706                              CLK_ROOT_SOURCE_SEL(0));
 707
 708         /*
 709          * 8MQ only supports two grades: consumer and industrial.
 710          * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
 711          */
 712         grade = get_cpu_temp_grade(NULL, NULL);
 713         if (!grade)
 714                 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
 715         else
 716                 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_800M);
 717
 718         /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
 719         clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
 720
 721         /*
 722          * According to ANAMIX SPEC
 723          * sys pll1 fixed at 800MHz
 724          * sys pll2 fixed at 1GHz
 725          * Here we only enable the outputs.
 726          */
 727         setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
 728                      SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
 729                      SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
 730                      SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
 731                      SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
 732
 733         setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
 734                      SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
 735                      SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
 736                      SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
 737                      SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
 738
 739         clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
 740                              CLK_ROOT_SOURCE_SEL(1));
 741
 742         init_wdog_clk();
 743         clock_enable(CCGR_TSENSOR, 1);
 744         clock_enable(CCGR_OCOTP, 1);
 745
 746         /* config GIC ROOT to sys_pll2_200m */
 747         clock_enable(CCGR_GIC, 0);
 748         clock_set_target_val(GIC_CLK_ROOT,
 749                              CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
 750         clock_enable(CCGR_GIC, 1);
 751
 752         return 0;
 753 }
 754 #endif
 755
 756 /*
 757  * Dump some clockes.
 758  */
 759 #ifndef CONFIG_SPL_BUILD
 760 static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
 761                                char *const argv[])
 762 {
 763         u32 freq;
 764
 765         freq = decode_frac_pll(ARM_PLL_CLK);
 766         printf("ARM_PLL    %8d MHz\n", freq / 1000000);
 767         freq = decode_sscg_pll(DRAM_PLL1_CLK);
 768         printf("DRAM_PLL    %8d MHz\n", freq / 1000000);
 769         freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
 770         printf("SYS_PLL1_800    %8d MHz\n", freq / 1000000);
 771         freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
 772         printf("SYS_PLL1_400    %8d MHz\n", freq / 1000000);
 773         freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
 774         printf("SYS_PLL1_266    %8d MHz\n", freq / 1000000);
 775         freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
 776         printf("SYS_PLL1_200    %8d MHz\n", freq / 1000000);
 777         freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
 778         printf("SYS_PLL1_160    %8d MHz\n", freq / 1000000);
 779         freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
 780         printf("SYS_PLL1_133    %8d MHz\n", freq / 1000000);
 781         freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
 782         printf("SYS_PLL1_100    %8d MHz\n", freq / 1000000);
 783         freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
 784         printf("SYS_PLL1_80    %8d MHz\n", freq / 1000000);
 785         freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
 786         printf("SYS_PLL1_40    %8d MHz\n", freq / 1000000);
 787         freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
 788         printf("SYS_PLL2_1000    %8d MHz\n", freq / 1000000);
 789         freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
 790         printf("SYS_PLL2_500    %8d MHz\n", freq / 1000000);
 791         freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
 792         printf("SYS_PLL2_333    %8d MHz\n", freq / 1000000);
 793         freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
 794         printf("SYS_PLL2_250    %8d MHz\n", freq / 1000000);
 795         freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
 796         printf("SYS_PLL2_200    %8d MHz\n", freq / 1000000);
 797         freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
 798         printf("SYS_PLL2_166    %8d MHz\n", freq / 1000000);
 799         freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
 800         printf("SYS_PLL2_125    %8d MHz\n", freq / 1000000);
 801         freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
 802         printf("SYS_PLL2_100    %8d MHz\n", freq / 1000000);
 803         freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
 804         printf("SYS_PLL2_50    %8d MHz\n", freq / 1000000);
 805         freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
 806         printf("SYS_PLL3       %8d MHz\n", freq / 1000000);
 807         freq = mxc_get_clock(UART1_CLK_ROOT);
 808         printf("UART1          %8d MHz\n", freq / 1000000);
 809         freq = mxc_get_clock(USDHC1_CLK_ROOT);
 810         printf("USDHC1         %8d MHz\n", freq / 1000000);
 811         freq = mxc_get_clock(QSPI_CLK_ROOT);
 812         printf("QSPI           %8d MHz\n", freq / 1000000);
 813         return 0;
 814 }
 815
 816 U_BOOT_CMD(
 817         clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
 818         "display clocks",
 819         ""
 820 );
 821 #endif