1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
5 * Peng Fan <peng.fan@nxp.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/sys_proto.h>
15 #include <linux/bitops.h>
16 #include <linux/delay.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
22 void enable_ocotp_clk(unsigned char enable)
24 clock_enable(CCGR_OCOTP, !!enable);
27 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
29 /* 0 - 3 is valid i2c num */
33 clock_enable(CCGR_I2C1 + i2c_num, !!enable);
38 #ifdef CONFIG_SPL_BUILD
39 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
40 PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
41 PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
42 PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
43 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
44 PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
45 PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
46 PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
47 PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
48 PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
49 PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
52 static int fracpll_configure(enum pll_clocks pll, u32 freq)
57 struct imx_int_pll_rate_table *rate;
59 for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
60 if (freq == imx8mm_fracpll_tbl[i].rate)
64 if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
65 printf("No matched freq table %u\n", freq);
69 rate = &imx8mm_fracpll_tbl[i];
73 setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
74 setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
75 writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
77 pll_base = &ana_pll->dram_pll_gnrl_ctl;
79 case ANATOP_VIDEO_PLL:
80 pll_base = &ana_pll->video_pll1_gnrl_ctl;
85 /* Bypass clock and set lock to pll output lock */
86 tmp = readl(pll_base);
88 writel(tmp, pll_base);
92 writel(tmp, pll_base);
94 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
95 (rate->sdiv << SDIV_SHIFT);
96 writel(div_val, pll_base + 4);
97 writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
103 writel(tmp, pll_base);
106 while (!(readl(pll_base) & LOCK_STATUS))
111 writel(tmp, pll_base);
116 void dram_pll_init(ulong pll_val)
118 fracpll_configure(ANATOP_DRAM_PLL, pll_val);
121 static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
122 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
124 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
126 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
130 void dram_enable_bypass(ulong clk_val)
133 struct dram_bypass_clk_setting *config;
135 for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
136 if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
140 if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
141 printf("No matched freq table %lu\n", clk_val);
145 config = &imx8mm_dram_bypass_tbl[i];
147 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
148 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
149 CLK_ROOT_PRE_DIV(config->alt_pre_div));
150 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
151 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
152 CLK_ROOT_PRE_DIV(config->apb_pre_div));
153 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
154 CLK_ROOT_SOURCE_SEL(1));
157 void dram_disable_bypass(void)
159 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
160 CLK_ROOT_SOURCE_SEL(0));
161 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
162 CLK_ROOT_SOURCE_SEL(4) |
163 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
167 void init_uart_clk(u32 index)
170 * set uart clock root
175 clock_enable(CCGR_UART1, 0);
176 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
177 CLK_ROOT_SOURCE_SEL(0));
178 clock_enable(CCGR_UART1, 1);
181 clock_enable(CCGR_UART2, 0);
182 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
183 CLK_ROOT_SOURCE_SEL(0));
184 clock_enable(CCGR_UART2, 1);
187 clock_enable(CCGR_UART3, 0);
188 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
189 CLK_ROOT_SOURCE_SEL(0));
190 clock_enable(CCGR_UART3, 1);
193 clock_enable(CCGR_UART4, 0);
194 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
195 CLK_ROOT_SOURCE_SEL(0));
196 clock_enable(CCGR_UART4, 1);
199 printf("Invalid uart index\n");
204 void init_wdog_clk(void)
206 clock_enable(CCGR_WDOG1, 0);
207 clock_enable(CCGR_WDOG2, 0);
208 clock_enable(CCGR_WDOG3, 0);
209 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
210 CLK_ROOT_SOURCE_SEL(0));
211 clock_enable(CCGR_WDOG1, 1);
212 clock_enable(CCGR_WDOG2, 1);
213 clock_enable(CCGR_WDOG3, 1);
221 * The gate is not exported to clk tree, so configure them here.
222 * According to ANAMIX SPEC
223 * sys pll1 fixed at 800MHz
224 * sys pll2 fixed at 1GHz
225 * Here we only enable the outputs.
227 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
228 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
229 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
230 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
231 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
232 INTPLL_DIV20_CLKE_MASK;
233 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
235 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
236 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
237 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
238 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
239 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
240 INTPLL_DIV20_CLKE_MASK;
241 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
243 /* config GIC to sys_pll2_100m */
244 clock_enable(CCGR_GIC, 0);
245 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
246 CLK_ROOT_SOURCE_SEL(3));
247 clock_enable(CCGR_GIC, 1);
249 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
250 CLK_ROOT_SOURCE_SEL(1));
252 clock_enable(CCGR_DDR1, 0);
253 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
254 CLK_ROOT_SOURCE_SEL(1));
255 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
256 CLK_ROOT_SOURCE_SEL(1));
257 clock_enable(CCGR_DDR1, 1);
261 clock_enable(CCGR_TEMP_SENSOR, 1);
263 clock_enable(CCGR_SEC_DEBUG, 1);
268 u32 imx_get_uartclk(void)
273 static u32 decode_intpll(enum clk_root_src intpll)
275 u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
276 u32 main_div, pre_div, post_div, div;
281 pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
282 pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
285 pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
286 pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
289 pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
290 pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
292 case SYSTEM_PLL1_800M_CLK:
293 case SYSTEM_PLL1_400M_CLK:
294 case SYSTEM_PLL1_266M_CLK:
295 case SYSTEM_PLL1_200M_CLK:
296 case SYSTEM_PLL1_160M_CLK:
297 case SYSTEM_PLL1_133M_CLK:
298 case SYSTEM_PLL1_100M_CLK:
299 case SYSTEM_PLL1_80M_CLK:
300 case SYSTEM_PLL1_40M_CLK:
301 pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
302 pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
304 case SYSTEM_PLL2_1000M_CLK:
305 case SYSTEM_PLL2_500M_CLK:
306 case SYSTEM_PLL2_333M_CLK:
307 case SYSTEM_PLL2_250M_CLK:
308 case SYSTEM_PLL2_200M_CLK:
309 case SYSTEM_PLL2_166M_CLK:
310 case SYSTEM_PLL2_125M_CLK:
311 case SYSTEM_PLL2_100M_CLK:
312 case SYSTEM_PLL2_50M_CLK:
313 pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
314 pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
316 case SYSTEM_PLL3_CLK:
317 pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
318 pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
324 /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
325 if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
328 if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
332 * When BYPASS is equal to 1, PLL enters the bypass mode
333 * regardless of the values of RESETB
335 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
338 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
339 puts("pll not locked\n");
347 case SYSTEM_PLL3_CLK:
348 case SYSTEM_PLL1_800M_CLK:
349 case SYSTEM_PLL2_1000M_CLK:
350 pll_clke_mask = INTPLL_CLKE_MASK;
354 case SYSTEM_PLL1_400M_CLK:
355 case SYSTEM_PLL2_500M_CLK:
356 pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
360 case SYSTEM_PLL1_266M_CLK:
361 case SYSTEM_PLL2_333M_CLK:
362 pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
366 case SYSTEM_PLL1_200M_CLK:
367 case SYSTEM_PLL2_250M_CLK:
368 pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
372 case SYSTEM_PLL1_160M_CLK:
373 case SYSTEM_PLL2_200M_CLK:
374 pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
378 case SYSTEM_PLL1_133M_CLK:
379 case SYSTEM_PLL2_166M_CLK:
380 pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
384 case SYSTEM_PLL1_100M_CLK:
385 case SYSTEM_PLL2_125M_CLK:
386 pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
390 case SYSTEM_PLL1_80M_CLK:
391 case SYSTEM_PLL2_100M_CLK:
392 pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
396 case SYSTEM_PLL1_40M_CLK:
397 case SYSTEM_PLL2_50M_CLK:
398 pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
405 if ((pll_gnrl_ctl & pll_clke_mask) == 0)
408 main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
409 INTPLL_MAIN_DIV_SHIFT;
410 pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
411 INTPLL_PRE_DIV_SHIFT;
412 post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
413 INTPLL_POST_DIV_SHIFT;
415 /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
416 freq = 24000000ULL * main_div;
417 return lldiv(freq, pre_div * (1 << post_div) * div);
420 static u32 decode_fracpll(enum clk_root_src frac_pll)
422 u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
423 u32 main_div, pre_div, post_div, k;
427 pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
428 pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
429 pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
432 pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
433 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0);
434 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1);
437 pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
438 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0);
439 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1);
442 pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
443 pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0);
444 pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
447 printf("Not supported\n");
451 /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
452 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
455 if ((pll_gnrl_ctl & RST_MASK) == 0)
458 * When BYPASS is equal to 1, PLL enters the bypass mode
459 * regardless of the values of RESETB
461 if (pll_gnrl_ctl & BYPASS_MASK)
464 if (!(pll_gnrl_ctl & LOCK_STATUS)) {
465 puts("pll not locked\n");
469 if (!(pll_gnrl_ctl & CLKE_MASK))
472 main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
474 pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
476 post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
479 k = pll_fdiv_ctl1 & KDIV_MASK;
481 return lldiv((main_div * 65536 + k) * 24000000ULL,
482 65536 * pre_div * (1 << post_div));
485 static u32 get_root_src_clk(enum clk_root_src root_src)
497 case SYSTEM_PLL1_800M_CLK:
498 case SYSTEM_PLL1_400M_CLK:
499 case SYSTEM_PLL1_266M_CLK:
500 case SYSTEM_PLL1_200M_CLK:
501 case SYSTEM_PLL1_160M_CLK:
502 case SYSTEM_PLL1_133M_CLK:
503 case SYSTEM_PLL1_100M_CLK:
504 case SYSTEM_PLL1_80M_CLK:
505 case SYSTEM_PLL1_40M_CLK:
506 case SYSTEM_PLL2_1000M_CLK:
507 case SYSTEM_PLL2_500M_CLK:
508 case SYSTEM_PLL2_333M_CLK:
509 case SYSTEM_PLL2_250M_CLK:
510 case SYSTEM_PLL2_200M_CLK:
511 case SYSTEM_PLL2_166M_CLK:
512 case SYSTEM_PLL2_125M_CLK:
513 case SYSTEM_PLL2_100M_CLK:
514 case SYSTEM_PLL2_50M_CLK:
515 case SYSTEM_PLL3_CLK:
516 return decode_intpll(root_src);
521 return decode_fracpll(root_src);
529 static u32 get_root_clk(enum clk_root_index clock_id)
531 enum clk_root_src root_src;
532 u32 post_podf, pre_podf, root_src_clk;
534 if (clock_root_enabled(clock_id) <= 0)
537 if (clock_get_prediv(clock_id, &pre_podf) < 0)
540 if (clock_get_postdiv(clock_id, &post_podf) < 0)
543 if (clock_get_src(clock_id, &root_src) < 0)
546 root_src_clk = get_root_src_clk(root_src);
548 return root_src_clk / (post_podf + 1) / (pre_podf + 1);
551 u32 mxc_get_clock(enum mxc_clock clk)
557 return get_root_clk(ARM_A53_CLK_ROOT);
559 clock_get_target_val(IPG_CLK_ROOT, &val);
561 return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
563 return get_root_clk(ECSPI1_CLK_ROOT);
565 return get_root_clk(USDHC1_CLK_ROOT);
567 return get_root_clk(USDHC2_CLK_ROOT);
569 return get_root_clk(USDHC3_CLK_ROOT);
571 return get_root_clk(I2C1_CLK_ROOT);
573 return get_root_clk(UART1_CLK_ROOT);
575 return get_root_clk(QSPI_CLK_ROOT);
577 printf("Unsupported mxc_clock %d\n", clk);
584 #ifdef CONFIG_FEC_MXC
585 int set_clk_enet(enum enet_freq type)
592 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
595 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
598 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
604 /* disable the clock first */
605 clock_enable(CCGR_ENET1, 0);
606 clock_enable(CCGR_SIM_ENET, 0);
608 /* set enet axi clock 266Mhz */
609 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
610 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
611 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
612 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
614 target = CLK_ROOT_ON | enet1_ref |
615 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
616 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
617 clock_set_target_val(ENET_REF_CLK_ROOT, target);
619 target = CLK_ROOT_ON |
620 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
621 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
622 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
623 clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
626 clock_enable(CCGR_SIM_ENET, 1);
627 clock_enable(CCGR_ENET1, 1);