arch/arm/mach-imx/imx8/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <cpu.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <asm/cache.h>
  14 #include <dm/device-internal.h>
  15 #include <dm/lists.h>
  16 #include <dm/uclass.h>
  17 #include <errno.h>
  18 #include <spl.h>
  19 #include <thermal.h>
  20 #include <asm/arch/sci/sci.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch-imx/cpu.h>
  23 #include <asm/armv8/cpu.h>
  24 #include <asm/armv8/mmu.h>
  25 #include <asm/setup.h>
  26 #include <asm/mach-imx/boot_mode.h>
  27 #include <spl.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define BT_PASSOVER_TAG 0x504F
  32 struct pass_over_info_t *get_pass_over_info(void)
  33 {
  34         struct pass_over_info_t *p =
  35                 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
  36
  37         if (p->barker != BT_PASSOVER_TAG ||
  38             p->len != sizeof(struct pass_over_info_t))
  39                 return NULL;
  40
  41         return p;
  42 }
  43
  44 int arch_cpu_init(void)
  45 {
  46 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
  47         spl_save_restore_data();
  48 #endif
  49
  50 #ifdef CONFIG_SPL_BUILD
  51         struct pass_over_info_t *pass_over;
  52
  53         if (is_soc_rev(CHIP_REV_A)) {
  54                 pass_over = get_pass_over_info();
  55                 if (pass_over && pass_over->g_ap_mu == 0) {
  56                         /*
  57                          * When ap_mu is 0, means the U-Boot booted
  58                          * from first container
  59                          */
  60                         sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
  61                 }
  62         }
  63 #endif
  64
  65         return 0;
  66 }
  67
  68 int arch_cpu_init_dm(void)
  69 {
  70         struct udevice *devp;
  71         int node, ret;
  72
  73         node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
  74
  75         ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
  76         if (ret) {
  77                 printf("could not get scu %d\n", ret);
  78                 return ret;
  79         }
  80
  81         if (is_imx8qm()) {
  82                 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
  83                                                     SC_PM_PW_MODE_ON);
  84                 if (ret)
  85                         return ret;
  86         }
  87
  88         return 0;
  89 }
  90
  91 int print_bootinfo(void)
  92 {
  93         enum boot_device bt_dev = get_boot_device();
  94
  95         puts("Boot:  ");
  96         switch (bt_dev) {
  97         case SD1_BOOT:
  98                 puts("SD0\n");
  99                 break;
 100         case SD2_BOOT:
 101                 puts("SD1\n");
 102                 break;
 103         case SD3_BOOT:
 104                 puts("SD2\n");
 105                 break;
 106         case MMC1_BOOT:
 107                 puts("MMC0\n");
 108                 break;
 109         case MMC2_BOOT:
 110                 puts("MMC1\n");
 111                 break;
 112         case MMC3_BOOT:
 113                 puts("MMC2\n");
 114                 break;
 115         case FLEXSPI_BOOT:
 116                 puts("FLEXSPI\n");
 117                 break;
 118         case SATA_BOOT:
 119                 puts("SATA\n");
 120                 break;
 121         case NAND_BOOT:
 122                 puts("NAND\n");
 123                 break;
 124         case USB_BOOT:
 125                 puts("USB\n");
 126                 break;
 127         default:
 128                 printf("Unknown device %u\n", bt_dev);
 129                 break;
 130         }
 131
 132         return 0;
 133 }
 134
 135 enum boot_device get_boot_device(void)
 136 {
 137         enum boot_device boot_dev = SD1_BOOT;
 138
 139         sc_rsrc_t dev_rsrc;
 140
 141         sc_misc_get_boot_dev(-1, &dev_rsrc);
 142
 143         switch (dev_rsrc) {
 144         case SC_R_SDHC_0:
 145                 boot_dev = MMC1_BOOT;
 146                 break;
 147         case SC_R_SDHC_1:
 148                 boot_dev = SD2_BOOT;
 149                 break;
 150         case SC_R_SDHC_2:
 151                 boot_dev = SD3_BOOT;
 152                 break;
 153         case SC_R_NAND:
 154                 boot_dev = NAND_BOOT;
 155                 break;
 156         case SC_R_FSPI_0:
 157                 boot_dev = FLEXSPI_BOOT;
 158                 break;
 159         case SC_R_SATA_0:
 160                 boot_dev = SATA_BOOT;
 161                 break;
 162         case SC_R_USB_0:
 163         case SC_R_USB_1:
 164         case SC_R_USB_2:
 165                 boot_dev = USB_BOOT;
 166                 break;
 167         default:
 168                 break;
 169         }
 170
 171         return boot_dev;
 172 }
 173
 174 #ifdef CONFIG_SERIAL_TAG
 175 #define FUSE_UNIQUE_ID_WORD0 16
 176 #define FUSE_UNIQUE_ID_WORD1 17
 177 void get_board_serial(struct tag_serialnr *serialnr)
 178 {
 179         sc_err_t err;
 180         u32 val1 = 0, val2 = 0;
 181         u32 word1, word2;
 182
 183         if (!serialnr)
 184                 return;
 185
 186         word1 = FUSE_UNIQUE_ID_WORD0;
 187         word2 = FUSE_UNIQUE_ID_WORD1;
 188
 189         err = sc_misc_otp_fuse_read(-1, word1, &val1);
 190         if (err != SC_ERR_NONE) {
 191                 printf("%s fuse %d read error: %d\n", __func__, word1, err);
 192                 return;
 193         }
 194
 195         err = sc_misc_otp_fuse_read(-1, word2, &val2);
 196         if (err != SC_ERR_NONE) {
 197                 printf("%s fuse %d read error: %d\n", __func__, word2, err);
 198                 return;
 199         }
 200         serialnr->low = val1;
 201         serialnr->high = val2;
 202 }
 203 #endif /*CONFIG_SERIAL_TAG*/
 204
 205 #ifdef CONFIG_ENV_IS_IN_MMC
 206 __weak int board_mmc_get_env_dev(int devno)
 207 {
 208         return CONFIG_SYS_MMC_ENV_DEV;
 209 }
 210
 211 int mmc_get_env_dev(void)
 212 {
 213         sc_rsrc_t dev_rsrc;
 214         int devno;
 215
 216         sc_misc_get_boot_dev(-1, &dev_rsrc);
 217
 218         switch (dev_rsrc) {
 219         case SC_R_SDHC_0:
 220                 devno = 0;
 221                 break;
 222         case SC_R_SDHC_1:
 223                 devno = 1;
 224                 break;
 225         case SC_R_SDHC_2:
 226                 devno = 2;
 227                 break;
 228         default:
 229                 /* If not boot from sd/mmc, use default value */
 230                 return CONFIG_SYS_MMC_ENV_DEV;
 231         }
 232
 233         return board_mmc_get_env_dev(devno);
 234 }
 235 #endif
 236
 237 #define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */
 238
 239 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
 240                             sc_faddr_t *addr_end)
 241 {
 242         sc_faddr_t start, end;
 243         int ret;
 244         bool owned;
 245
 246         owned = sc_rm_is_memreg_owned(-1, mr);
 247         if (owned) {
 248                 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
 249                 if (ret) {
 250                         printf("Memreg get info failed, %d\n", ret);
 251                         return -EINVAL;
 252                 }
 253                 debug("0x%llx -- 0x%llx\n", start, end);
 254                 *addr_start = start;
 255                 *addr_end = end;
 256
 257                 return 0;
 258         }
 259
 260         return -EINVAL;
 261 }
 262
 263 phys_size_t get_effective_memsize(void)
 264 {
 265         sc_rm_mr_t mr;
 266         sc_faddr_t start, end, end1, start_aligned;
 267         int err;
 268
 269         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 270
 271         for (mr = 0; mr < 64; mr++) {
 272                 err = get_owned_memreg(mr, &start, &end);
 273                 if (!err) {
 274                         start_aligned = roundup(start, MEMSTART_ALIGNMENT);
 275                         /* Too small memory region, not use it */
 276                         if (start_aligned > end)
 277                                 continue;
 278
 279                         /* Find the memory region runs the U-Boot */
 280                         if (start >= PHYS_SDRAM_1 && start <= end1 &&
 281                             (start <= CONFIG_SYS_TEXT_BASE &&
 282                             end >= CONFIG_SYS_TEXT_BASE)) {
 283                                 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
 284                                     PHYS_SDRAM_1_SIZE))
 285                                         return (end - PHYS_SDRAM_1 + 1);
 286                                 else
 287                                         return PHYS_SDRAM_1_SIZE;
 288                         }
 289                 }
 290         }
 291
 292         return PHYS_SDRAM_1_SIZE;
 293 }
 294
 295 int dram_init(void)
 296 {
 297         sc_rm_mr_t mr;
 298         sc_faddr_t start, end, end1, end2;
 299         int err;
 300
 301         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 302         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 303         for (mr = 0; mr < 64; mr++) {
 304                 err = get_owned_memreg(mr, &start, &end);
 305                 if (!err) {
 306                         start = roundup(start, MEMSTART_ALIGNMENT);
 307                         /* Too small memory region, not use it */
 308                         if (start > end)
 309                                 continue;
 310
 311                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 312                                 if ((end + 1) <= end1)
 313                                         gd->ram_size += end - start + 1;
 314                                 else
 315                                         gd->ram_size += end1 - start;
 316                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 317                                 if ((end + 1) <= end2)
 318                                         gd->ram_size += end - start + 1;
 319                                 else
 320                                         gd->ram_size += end2 - start;
 321                         }
 322                 }
 323         }
 324
 325         /* If error, set to the default value */
 326         if (!gd->ram_size) {
 327                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 328                 gd->ram_size += PHYS_SDRAM_2_SIZE;
 329         }
 330         return 0;
 331 }
 332
 333 static void dram_bank_sort(int current_bank)
 334 {
 335         phys_addr_t start;
 336         phys_size_t size;
 337
 338         while (current_bank > 0) {
 339                 if (gd->bd->bi_dram[current_bank - 1].start >
 340                     gd->bd->bi_dram[current_bank].start) {
 341                         start = gd->bd->bi_dram[current_bank - 1].start;
 342                         size = gd->bd->bi_dram[current_bank - 1].size;
 343
 344                         gd->bd->bi_dram[current_bank - 1].start =
 345                                 gd->bd->bi_dram[current_bank].start;
 346                         gd->bd->bi_dram[current_bank - 1].size =
 347                                 gd->bd->bi_dram[current_bank].size;
 348
 349                         gd->bd->bi_dram[current_bank].start = start;
 350                         gd->bd->bi_dram[current_bank].size = size;
 351                 }
 352                 current_bank--;
 353         }
 354 }
 355
 356 int dram_init_banksize(void)
 357 {
 358         sc_rm_mr_t mr;
 359         sc_faddr_t start, end, end1, end2;
 360         int i = 0;
 361         int err;
 362
 363         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 364         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 365
 366         for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
 367                 err = get_owned_memreg(mr, &start, &end);
 368                 if (!err) {
 369                         start = roundup(start, MEMSTART_ALIGNMENT);
 370                         if (start > end) /* Small memory region, no use it */
 371                                 continue;
 372
 373                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 374                                 gd->bd->bi_dram[i].start = start;
 375
 376                                 if ((end + 1) <= end1)
 377                                         gd->bd->bi_dram[i].size =
 378                                                 end - start + 1;
 379                                 else
 380                                         gd->bd->bi_dram[i].size = end1 - start;
 381
 382                                 dram_bank_sort(i);
 383                                 i++;
 384                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 385                                 gd->bd->bi_dram[i].start = start;
 386
 387                                 if ((end + 1) <= end2)
 388                                         gd->bd->bi_dram[i].size =
 389                                                 end - start + 1;
 390                                 else
 391                                         gd->bd->bi_dram[i].size = end2 - start;
 392
 393                                 dram_bank_sort(i);
 394                                 i++;
 395                         }
 396                 }
 397         }
 398
 399         /* If error, set to the default value */
 400         if (!i) {
 401                 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 402                 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 403                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 404                 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 405         }
 406
 407         return 0;
 408 }
 409
 410 static u64 get_block_attrs(sc_faddr_t addr_start)
 411 {
 412         u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
 413                 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 414
 415         if ((addr_start >= PHYS_SDRAM_1 &&
 416              addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
 417             (addr_start >= PHYS_SDRAM_2 &&
 418              addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
 419                 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
 420
 421         return attr;
 422 }
 423
 424 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
 425 {
 426         sc_faddr_t end1, end2;
 427
 428         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 429         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 430
 431         if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
 432                 if ((addr_end + 1) > end1)
 433                         return end1 - addr_start;
 434         } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
 435                 if ((addr_end + 1) > end2)
 436                         return end2 - addr_start;
 437         }
 438
 439         return (addr_end - addr_start + 1);
 440 }
 441
 442 #define MAX_PTE_ENTRIES 512
 443 #define MAX_MEM_MAP_REGIONS 16
 444
 445 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
 446 struct mm_region *mem_map = imx8_mem_map;
 447
 448 void enable_caches(void)
 449 {
 450         sc_rm_mr_t mr;
 451         sc_faddr_t start, end;
 452         int err, i;
 453
 454         /* Create map for registers access from 0x1c000000 to 0x80000000*/
 455         imx8_mem_map[0].virt = 0x1c000000UL;
 456         imx8_mem_map[0].phys = 0x1c000000UL;
 457         imx8_mem_map[0].size = 0x64000000UL;
 458         imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 459                          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 460
 461         i = 1;
 462         for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
 463                 err = get_owned_memreg(mr, &start, &end);
 464                 if (!err) {
 465                         imx8_mem_map[i].virt = start;
 466                         imx8_mem_map[i].phys = start;
 467                         imx8_mem_map[i].size = get_block_size(start, end);
 468                         imx8_mem_map[i].attrs = get_block_attrs(start);
 469                         i++;
 470                 }
 471         }
 472
 473         if (i < MAX_MEM_MAP_REGIONS) {
 474                 imx8_mem_map[i].size = 0;
 475                 imx8_mem_map[i].attrs = 0;
 476         } else {
 477                 puts("Error, need more MEM MAP REGIONS reserved\n");
 478                 icache_enable();
 479                 return;
 480         }
 481
 482         for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
 483                 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
 484                       i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
 485                       imx8_mem_map[i].size, imx8_mem_map[i].attrs);
 486         }
 487
 488         icache_enable();
 489         dcache_enable();
 490 }
 491
 492 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 493 u64 get_page_table_size(void)
 494 {
 495         u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
 496         u64 size = 0;
 497
 498         /*
 499          * For each memory region, the max table size:
 500          * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
 501          */
 502         size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
 503
 504         /*
 505          * We need to duplicate our page table once to have an emergency pt to
 506          * resort to when splitting page tables later on
 507          */
 508         size *= 2;
 509
 510         /*
 511          * We may need to split page tables later on if dcache settings change,
 512          * so reserve up to 4 (random pick) page tables for that.
 513          */
 514         size += one_pt * 4;
 515
 516         return size;
 517 }
 518 #endif
 519
 520 #if defined(CONFIG_IMX8QM)
 521 #define FUSE_MAC0_WORD0 452
 522 #define FUSE_MAC0_WORD1 453
 523 #define FUSE_MAC1_WORD0 454
 524 #define FUSE_MAC1_WORD1 455
 525 #elif defined(CONFIG_IMX8QXP)
 526 #define FUSE_MAC0_WORD0 708
 527 #define FUSE_MAC0_WORD1 709
 528 #define FUSE_MAC1_WORD0 710
 529 #define FUSE_MAC1_WORD1 711
 530 #endif
 531
 532 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 533 {
 534         u32 word[2], val[2] = {};
 535         int i, ret;
 536
 537         if (dev_id == 0) {
 538                 word[0] = FUSE_MAC0_WORD0;
 539                 word[1] = FUSE_MAC0_WORD1;
 540         } else {
 541                 word[0] = FUSE_MAC1_WORD0;
 542                 word[1] = FUSE_MAC1_WORD1;
 543         }
 544
 545         for (i = 0; i < 2; i++) {
 546                 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
 547                 if (ret < 0)
 548                         goto err;
 549         }
 550
 551         mac[0] = val[0];
 552         mac[1] = val[0] >> 8;
 553         mac[2] = val[0] >> 16;
 554         mac[3] = val[0] >> 24;
 555         mac[4] = val[1];
 556         mac[5] = val[1] >> 8;
 557
 558         debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
 559               __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 560         return;
 561 err:
 562         printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
 563 }
 564
 565 u32 get_cpu_rev(void)
 566 {
 567         u32 id = 0, rev = 0;
 568         int ret;
 569
 570         ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
 571         if (ret)
 572                 return 0;
 573
 574         rev = (id >> 5)  & 0xf;
 575         id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */
 576
 577         return (id << 12) | rev;
 578 }
 579
 580 void board_boot_order(u32 *spl_boot_list)
 581 {
 582         spl_boot_list[0] = spl_boot_device();
 583
 584         if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
 585                 /* Check whether we own the flexspi0, if not, use NOR boot */
 586                 if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0))
 587                         spl_boot_list[0] = BOOT_DEVICE_NOR;
 588         }
 589 }
 590
 591 bool m4_parts_booted(void)
 592 {
 593         sc_rm_pt_t m4_parts[2];
 594         int err;
 595
 596         err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]);
 597         if (err) {
 598                 printf("%s get resource [%d] owner error: %d\n", __func__,
 599                        SC_R_M4_0_PID0, err);
 600                 return false;
 601         }
 602
 603         if (sc_pm_is_partition_started(-1, m4_parts[0]))
 604                 return true;
 605
 606         if (is_imx8qm()) {
 607                 err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]);
 608                 if (err) {
 609                         printf("%s get resource [%d] owner error: %d\n",
 610                                __func__, SC_R_M4_1_PID0, err);
 611                         return false;
 612                 }
 613
 614                 if (sc_pm_is_partition_started(-1, m4_parts[1]))
 615                         return true;
 616         }
 617
 618         return false;
 619 }