arch/arm/mach-exynos/include/mach/dp_info.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2012 Samsung Electronics
   4  *
   5  * Author: Donghwa Lee <dh09.lee@samsung.com>
   6  */
   7
   8 #ifndef _DP_INFO_H
   9 #define _DP_INFO_H
  10
  11 #define msleep(a)                       udelay(a * 1000)
  12
  13 #define DP_TIMEOUT_LOOP_COUNT           100
  14 #define MAX_CR_LOOP                     5
  15 #define MAX_EQ_LOOP                     4
  16
  17 #define EXYNOS_DP_SUCCESS               0
  18
  19 enum {
  20         DP_DISABLE,
  21         DP_ENABLE,
  22 };
  23
  24 struct edp_disp_info {
  25         char *name;
  26         unsigned int h_total;
  27         unsigned int h_res;
  28         unsigned int h_sync_width;
  29         unsigned int h_back_porch;
  30         unsigned int h_front_porch;
  31         unsigned int v_total;
  32         unsigned int v_res;
  33         unsigned int v_sync_width;
  34         unsigned int v_back_porch;
  35         unsigned int v_front_porch;
  36
  37         unsigned int v_sync_rate;
  38 };
  39
  40 struct edp_link_train_info {
  41         unsigned int lt_status;
  42
  43         unsigned int ep_loop;
  44         unsigned int cr_loop[4];
  45
  46 };
  47
  48 struct edp_video_info {
  49         unsigned int master_mode;
  50         unsigned int bist_mode;
  51         unsigned int bist_pattern;
  52
  53         unsigned int h_sync_polarity;
  54         unsigned int v_sync_polarity;
  55         unsigned int interlaced;
  56
  57         unsigned int color_space;
  58         unsigned int dynamic_range;
  59         unsigned int ycbcr_coeff;
  60         unsigned int color_depth;
  61 };
  62
  63 struct exynos_dp_priv {
  64         struct edp_disp_info disp_info;
  65         struct edp_link_train_info lt_info;
  66         struct edp_video_info video_info;
  67
  68         /*below info get from panel during training*/
  69         unsigned char lane_bw;
  70         unsigned char lane_cnt;
  71         unsigned char dpcd_rev;
  72         /*support enhanced frame cap */
  73         unsigned char dpcd_efc;
  74         struct exynos_dp *regs;
  75 };
  76
  77 enum analog_power_block {
  78         AUX_BLOCK,
  79         CH0_BLOCK,
  80         CH1_BLOCK,
  81         CH2_BLOCK,
  82         CH3_BLOCK,
  83         ANALOG_TOTAL,
  84         POWER_ALL
  85 };
  86
  87 enum pll_status {
  88         PLL_UNLOCKED = 0,
  89         PLL_LOCKED
  90 };
  91
  92 enum {
  93         COLOR_RGB,
  94         COLOR_YCBCR422,
  95         COLOR_YCBCR444
  96 };
  97
  98 enum {
  99         VESA,
 100         CEA
 101 };
 102
 103 enum {
 104         COLOR_YCBCR601,
 105         COLOR_YCBCR709
 106 };
 107
 108 enum {
 109         COLOR_6,
 110         COLOR_8,
 111         COLOR_10,
 112         COLOR_12
 113 };
 114
 115 enum {
 116         DP_LANE_BW_1_62 = 0x06,
 117         DP_LANE_BW_2_70 = 0x0a,
 118 };
 119
 120 enum {
 121         DP_LANE_CNT_1 = 1,
 122         DP_LANE_CNT_2 = 2,
 123         DP_LANE_CNT_4 = 4,
 124 };
 125
 126 enum {
 127         DP_DPCD_REV_10 = 0x10,
 128         DP_DPCD_REV_11 = 0x11,
 129 };
 130
 131 enum {
 132         DP_LT_NONE,
 133         DP_LT_START,
 134         DP_LT_CR,
 135         DP_LT_ET,
 136         DP_LT_FINISHED,
 137         DP_LT_FAIL,
 138 };
 139
 140 enum  {
 141         PRE_EMPHASIS_LEVEL_0,
 142         PRE_EMPHASIS_LEVEL_1,
 143         PRE_EMPHASIS_LEVEL_2,
 144         PRE_EMPHASIS_LEVEL_3,
 145 };
 146
 147 enum {
 148         PRBS7,
 149         D10_2,
 150         TRAINING_PTN1,
 151         TRAINING_PTN2,
 152         DP_NONE
 153 };
 154
 155 enum {
 156         VOLTAGE_LEVEL_0,
 157         VOLTAGE_LEVEL_1,
 158         VOLTAGE_LEVEL_2,
 159         VOLTAGE_LEVEL_3,
 160 };
 161
 162 enum pattern_type {
 163         NO_PATTERN,
 164         COLOR_RAMP,
 165         BALCK_WHITE_V_LINES,
 166         COLOR_SQUARE,
 167         INVALID_PATTERN,
 168         COLORBAR_32,
 169         COLORBAR_64,
 170         WHITE_GRAY_BALCKBAR_32,
 171         WHITE_GRAY_BALCKBAR_64,
 172         MOBILE_WHITEBAR_32,
 173         MOBILE_WHITEBAR_64
 174 };
 175
 176 enum {
 177         CALCULATED_M,
 178         REGISTER_M
 179 };
 180
 181 enum {
 182         VIDEO_TIMING_FROM_CAPTURE,
 183         VIDEO_TIMING_FROM_REGISTER
 184 };
 185
 186
 187 struct exynos_dp_platform_data {
 188         struct exynos_dp_priv *edp_dev_info;
 189 };
 190
 191 #ifdef CONFIG_EXYNOS_DP
 192 unsigned int exynos_init_dp(void);
 193 #else
 194 unsigned int exynos_init_dp(void)
 195 {
 196         return 0;
 197 }
 198 #endif
 199
 200 #include <linux/delay.h>
 201 #endif /* _DP_INFO_H */