1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Google, Inc
12 #include <asm/arch/timer.h>
13 #include <asm/arch/wdt.h>
14 #include <linux/err.h>
15 #include <dm/uclass.h>
18 * Second Watchdog Timer by default is configured
19 * to trigger secondary boot source.
21 #define AST_2ND_BOOT_WDT 1
24 * Third Watchdog Timer by default is configured
25 * to toggle Flash address mode switch before reset.
27 #define AST_FLASH_ADDR_DETECT_WDT 2
29 DECLARE_GLOBAL_DATA_PTR;
31 void lowlevel_init(void)
34 * These two watchdogs need to be stopped as soon as possible,
35 * otherwise the board might hang. By default they are set to
36 * a very short timeout and even simple debug write to serial
37 * console early in the init process might cause them to fire.
39 struct ast_wdt *flash_addr_wdt =
40 (struct ast_wdt *)(WDT_BASE +
41 sizeof(struct ast_wdt) *
42 AST_FLASH_ADDR_DETECT_WDT);
44 clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN);
46 #ifndef CONFIG_FIRMWARE_2ND_BOOT
47 struct ast_wdt *sec_boot_wdt =
48 (struct ast_wdt *)(WDT_BASE +
49 sizeof(struct ast_wdt) *
52 clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN);
58 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
69 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
71 debug("DRAM FAIL1\r\n");
75 ret = ram_get_info(dev, &ram);
77 debug("DRAM FAIL2\r\n");
81 gd->ram_size = ram.size;