arch/arm/include/asm/ti-common/keystone_net.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * emac definitions for keystone2 devices
   4  *
   5  * (C) Copyright 2012-2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #ifndef _KEYSTONE_NET_H_
  10 #define _KEYSTONE_NET_H_
  11
  12 #include <asm/io.h>
  13 #include <phy.h>
  14 #ifndef __ASSEMBLY__
  15 #include <linux/bitops.h>
  16 #endif
  17
  18 /* EMAC */
  19 #ifdef CONFIG_KSNET_NETCP_V1_0
  20
  21 #define GBETH_BASE                      (CONFIG_KSNET_NETCP_BASE + 0x00090000)
  22 #define EMAC_EMACSL_BASE_ADDR           (GBETH_BASE + 0x900)
  23 #define EMAC_MDIO_BASE_ADDR             (GBETH_BASE + 0x300)
  24 #define EMAC_SGMII_BASE_ADDR            (GBETH_BASE + 0x100)
  25 #define DEVICE_EMACSL_BASE(x)           (EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
  26
  27 /* Register offsets */
  28 #define CPGMACSL_REG_CTL                0x04
  29 #define CPGMACSL_REG_STATUS             0x08
  30 #define CPGMACSL_REG_RESET              0x0c
  31 #define CPGMACSL_REG_MAXLEN             0x10
  32
  33 #elif defined CONFIG_KSNET_NETCP_V1_5
  34
  35 #define GBETH_BASE                      (CONFIG_KSNET_NETCP_BASE + 0x00200000)
  36 #define CPGMACSL_REG_RX_PRI_MAP         0x020
  37 #define EMAC_EMACSL_BASE_ADDR           (GBETH_BASE + 0x22000)
  38 #define EMAC_MDIO_BASE_ADDR             (GBETH_BASE + 0x00f00)
  39 #define EMAC_SGMII_BASE_ADDR            (GBETH_BASE + 0x00100)
  40 #define DEVICE_EMACSL_BASE(x)           (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
  41
  42 /* Register offsets */
  43 #define CPGMACSL_REG_CTL                0x330
  44 #define CPGMACSL_REG_STATUS             0x334
  45 #define CPGMACSL_REG_RESET              0x338
  46 #define CPGMACSL_REG_MAXLEN             0x024
  47
  48 #endif
  49
  50 #define KEYSTONE2_EMAC_GIG_ENABLE
  51
  52 #define MAC_ID_BASE_ADDR                CONFIG_KSNET_MAC_ID_BASE
  53
  54 /* MDIO module input frequency */
  55 #ifdef CONFIG_SOC_K2G
  56 #define EMAC_MDIO_BUS_FREQ              (ks_clk_get_rate(sys_clk0_3_clk))
  57 #else
  58 #define EMAC_MDIO_BUS_FREQ              (ks_clk_get_rate(pass_pll_clk))
  59 #endif
  60 /* MDIO clock output frequency */
  61 #define EMAC_MDIO_CLOCK_FREQ            2500000 /* 2.5 MHz */
  62
  63 #define EMAC_MACCONTROL_MIIEN_ENABLE            0x20
  64 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE       0x1
  65 #define EMAC_MACCONTROL_GIGABIT_ENABLE          BIT(7)
  66 #define EMAC_MACCONTROL_GIGFORCE                BIT(17)
  67 #define EMAC_MACCONTROL_RMIISPEED_100           BIT(15)
  68
  69 #define EMAC_MIN_ETHERNET_PKT_SIZE              60
  70
  71 struct mac_sl_cfg {
  72         u_int32_t max_rx_len;   /* Maximum receive packet length. */
  73         u_int32_t ctl;          /* Control bitfield */
  74 };
  75
  76 /**
  77  * Definition: Control bitfields used in the ctl field of mac_sl_cfg
  78  */
  79 #define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES     BIT(24)
  80 #define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES       BIT(23)
  81 #define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES       BIT(22)
  82 #define GMACSL_RX_ENABLE_EXT_CTL                BIT(18)
  83 #define GMACSL_RX_ENABLE_GIG_FORCE              BIT(17)
  84 #define GMACSL_RX_ENABLE_IFCTL_B                BIT(16)
  85 #define GMACSL_RX_ENABLE_IFCTL_A                BIT(15)
  86 #define GMACSL_RX_ENABLE_CMD_IDLE               BIT(11)
  87 #define GMACSL_TX_ENABLE_SHORT_GAP              BIT(10)
  88 #define GMACSL_ENABLE_GIG_MODE                  BIT(7)
  89 #define GMACSL_TX_ENABLE_PACE                   BIT(6)
  90 #define GMACSL_ENABLE                           BIT(5)
  91 #define GMACSL_TX_ENABLE_FLOW_CTL               BIT(4)
  92 #define GMACSL_RX_ENABLE_FLOW_CTL               BIT(3)
  93 #define GMACSL_ENABLE_LOOPBACK                  BIT(1)
  94 #define GMACSL_ENABLE_FULL_DUPLEX               BIT(0)
  95
  96 /* EMAC SL function return values */
  97 #define GMACSL_RET_OK                           0
  98 #define GMACSL_RET_INVALID_PORT                 -1
  99 #define GMACSL_RET_WARN_RESET_INCOMPLETE        -2
 100 #define GMACSL_RET_WARN_MAXLEN_TOO_BIG          -3
 101 #define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE     -4
 102
 103 /* EMAC SL register definitions */
 104 #define DEVICE_EMACSL_RESET_POLL_COUNT          100
 105
 106 /* Soft reset register values */
 107 #define CPGMAC_REG_RESET_VAL_RESET_MASK         BIT(0)
 108 #define CPGMAC_REG_RESET_VAL_RESET              BIT(0)
 109 #define CPGMAC_REG_MAXLEN_LEN                   0x3fff
 110
 111 /* CPSW */
 112 /* Control bitfields */
 113 #define CPSW_CTL_P2_PASS_PRI_TAGGED             BIT(5)
 114 #define CPSW_CTL_P1_PASS_PRI_TAGGED             BIT(4)
 115 #define CPSW_CTL_P0_PASS_PRI_TAGGED             BIT(3)
 116 #define CPSW_CTL_P0_ENABLE                      BIT(2)
 117 #define CPSW_CTL_VLAN_AWARE                     BIT(1)
 118 #define CPSW_CTL_FIFO_LOOPBACK                  BIT(0)
 119
 120 #define DEVICE_CPSW_NUM_PORTS                   CONFIG_KSNET_CPSW_NUM_PORTS
 121 #define DEVICE_N_GMACSL_PORTS                   (DEVICE_CPSW_NUM_PORTS - 1)
 122
 123 #ifdef CONFIG_KSNET_NETCP_V1_0
 124
 125 #define DEVICE_CPSW_BASE                        (GBETH_BASE + 0x800)
 126 #define CPSW_REG_CTL                            0x004
 127 #define CPSW_REG_STAT_PORT_EN                   0x00c
 128 #define CPSW_REG_MAXLEN                         0x040
 129 #define CPSW_REG_ALE_CONTROL                    0x608
 130 #define CPSW_REG_ALE_PORTCTL(x)                 (0x640 + (x) * 4)
 131 #define CPSW_REG_VAL_STAT_ENABLE_ALL            0xf
 132
 133 #elif defined CONFIG_KSNET_NETCP_V1_5
 134
 135 #define DEVICE_CPSW_BASE                        (GBETH_BASE + 0x20000)
 136 #define CPSW_REG_CTL                            0x00004
 137 #define CPSW_REG_STAT_PORT_EN                   0x00014
 138 #define CPSW_REG_MAXLEN                         0x01024
 139 #define CPSW_REG_ALE_CONTROL                    0x1e008
 140 #define CPSW_REG_ALE_PORTCTL(x)                 (0x1e040 + (x) * 4)
 141 #define CPSW_REG_VAL_STAT_ENABLE_ALL            0x1ff
 142
 143 #endif
 144
 145 #define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE   ((u_int32_t)0xc0000000)
 146 #define CPSW_REG_VAL_ALE_CTL_BYPASS             ((u_int32_t)0x00000010)
 147 #define CPSW_REG_VAL_PORTCTL_FORWARD_MODE       0x3
 148
 149 #define target_get_switch_ctl()                 CPSW_CTL_P0_ENABLE
 150 #define SWITCH_MAX_PKT_SIZE                     9000
 151
 152 /* SGMII */
 153 #define SGMII_REG_STATUS_LOCK                   BIT(4)
 154 #define SGMII_REG_STATUS_LINK                   BIT(0)
 155 #define SGMII_REG_STATUS_AUTONEG                BIT(2)
 156 #define SGMII_REG_CONTROL_AUTONEG               BIT(0)
 157 #define SGMII_REG_CONTROL_MASTER                BIT(5)
 158 #define SGMII_REG_MR_ADV_ENABLE                 BIT(0)
 159 #define SGMII_REG_MR_ADV_LINK                   BIT(15)
 160 #define SGMII_REG_MR_ADV_FULL_DUPLEX            BIT(12)
 161 #define SGMII_REG_MR_ADV_GIG_MODE               BIT(11)
 162
 163 #define SGMII_LINK_MAC_MAC_AUTONEG              0
 164 #define SGMII_LINK_MAC_PHY                      1
 165 #define SGMII_LINK_MAC_MAC_FORCED               2
 166 #define SGMII_LINK_MAC_FIBER                    3
 167 #define SGMII_LINK_MAC_PHY_FORCED               4
 168
 169 #ifdef CONFIG_KSNET_NETCP_V1_0
 170 #define SGMII_OFFSET(x)         ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
 171 #elif defined CONFIG_KSNET_NETCP_V1_5
 172 #define SGMII_OFFSET(x)         ((x) * 0x100)
 173 #endif
 174
 175 #define SGMII_IDVER_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
 176 #define SGMII_SRESET_REG(x)     (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
 177 #define SGMII_CTL_REG(x)        (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
 178 #define SGMII_STATUS_REG(x)     (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
 179 #define SGMII_MRADV_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
 180 #define SGMII_LPADV_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
 181 #define SGMII_TXCFG_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
 182 #define SGMII_RXCFG_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
 183 #define SGMII_AUXCFG_REG(x)     (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
 184
 185 /* RGMII */
 186 #define RGMII_REG_STATUS_LINK           BIT(0)
 187
 188 #define RGMII_STATUS_REG                (GBETH_BASE + 0x18)
 189
 190 /* PSS */
 191 #ifdef CONFIG_KSNET_NETCP_V1_0
 192
 193 #define DEVICE_PSTREAM_CFG_REG_ADDR     (CONFIG_KSNET_NETCP_BASE + 0x604)
 194 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI       0x06060606
 195 #define hw_config_streaming_switch()\
 196         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
 197
 198 #elif defined CONFIG_KSNET_NETCP_V1_5
 199
 200 #define DEVICE_PSTREAM_CFG_REG_ADDR     (CONFIG_KSNET_NETCP_BASE + 0x500)
 201 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI       0x0
 202
 203 #define hw_config_streaming_switch()\
 204         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 205                DEVICE_PSTREAM_CFG_REG_ADDR);\
 206         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 207                DEVICE_PSTREAM_CFG_REG_ADDR+4);\
 208         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 209                DEVICE_PSTREAM_CFG_REG_ADDR+8);\
 210         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 211                DEVICE_PSTREAM_CFG_REG_ADDR+12);
 212
 213 #endif
 214
 215 /* EMAC MDIO Registers Structure */
 216 struct mdio_regs {
 217         u32 version;
 218         u32 control;
 219         u32 alive;
 220         u32 link;
 221         u32 linkintraw;
 222         u32 linkintmasked;
 223         u32 rsvd0[2];
 224         u32 userintraw;
 225         u32 userintmasked;
 226         u32 userintmaskset;
 227         u32 userintmaskclear;
 228         u32 rsvd1[20];
 229         u32 useraccess0;
 230         u32 userphysel0;
 231         u32 useraccess1;
 232         u32 userphysel1;
 233 };
 234
 235 #endif  /* _KEYSTONE_NET_H_ */