arch/arm/include/asm/arch-tegra124/flow.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2010-2013
   4  * NVIDIA Corporation <www.nvidia.com>
   5  */
   6
   7 #ifndef _TEGRA124_FLOW_H_
   8 #define _TEGRA124_FLOW_H_
   9
  10 #ifndef __ASSEMBLY__
  11 #include <linux/bitops.h>
  12 #endif
  13
  14 struct flow_ctlr {
  15         u32 halt_cpu_events;    /* offset 0x00 */
  16         u32 halt_cop_events;    /* offset 0x04 */
  17         u32 cpu_csr;            /* offset 0x08 */
  18         u32 cop_csr;            /* offset 0x0c */
  19         u32 xrq_events;         /* offset 0x10 */
  20         u32 halt_cpu1_events;   /* offset 0x14 */
  21         u32 cpu1_csr;           /* offset 0x18 */
  22         u32 halt_cpu2_events;   /* offset 0x1c */
  23         u32 cpu2_csr;           /* offset 0x20 */
  24         u32 halt_cpu3_events;   /* offset 0x24 */
  25         u32 cpu3_csr;           /* offset 0x28 */
  26         u32 cluster_control;    /* offset 0x2c */
  27         u32 halt_cop1_events;   /* offset 0x30 */
  28         u32 halt_cop1_csr;      /* offset 0x34 */
  29         u32 cpu_pwr_csr;        /* offset 0x38 */
  30         u32 mpid;               /* offset 0x3c */
  31         u32 ram_repair;         /* offset 0x40 */
  32         u32 flow_dbg_sel;       /* offset 0x44 */
  33         u32 flow_dbg_cnt0;      /* offset 0x48 */
  34         u32 flow_dbg_cnt1;      /* offset 0x4c */
  35         u32 flow_dbg_qual;      /* offset 0x50 */
  36         u32 flow_ctrl_spare;    /* offset 0x54 */
  37         u32 ram_repair_cluster1;/* offset 0x58 */
  38 };
  39
  40 /* HALT_COP_EVENTS_0, 0x04 */
  41 #define EVENT_MSEC              (1 << 24)
  42 #define EVENT_USEC              (1 << 25)
  43 #define EVENT_JTAG              (1 << 28)
  44 #define EVENT_MODE_STOP         (2 << 29)
  45
  46 /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
  47 #define ACTIVE_LP               (1 << 0)
  48
  49 /* CPUn_CSR_0 */
  50 #define CSR_ENABLE              (1 << 0)
  51 #define CSR_IMMEDIATE_WAKE      (1 << 3)
  52 #define CSR_WAIT_WFI_SHIFT      8
  53 #define CSR_PWR_OFF_STS         (1 << 16)
  54
  55 #define RAM_REPAIR_REQ          BIT(0)
  56 #define RAM_REPAIR_STS          BIT(1)
  57 #define RAM_REPAIR_BYPASS_EN    BIT(2)
  58
  59 #endif  /*  _TEGRA124_FLOW_H_ */