arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h

   1 /*
   2  * H6 dram controller register and constant defines
   3  *
   4  * (C) Copyright 2017  Icenowy Zheng <icenowy@aosc.io>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _SUNXI_DRAM_SUN50I_H6_H
  10 #define _SUNXI_DRAM_SUN50I_H6_H
  11
  12 #include <stdbool.h>
  13 #ifndef __ASSEMBLY__
  14 #include <linux/bitops.h>
  15 #endif
  16
  17 enum sunxi_dram_type {
  18         SUNXI_DRAM_TYPE_DDR3 = 3,
  19         SUNXI_DRAM_TYPE_DDR4,
  20         SUNXI_DRAM_TYPE_LPDDR2 = 6,
  21         SUNXI_DRAM_TYPE_LPDDR3,
  22 };
  23
  24 static inline bool sunxi_dram_is_lpddr(int type)
  25 {
  26         return type >= SUNXI_DRAM_TYPE_LPDDR2;
  27 }
  28
  29 /*
  30  * The following information is mainly retrieved by disassembly and some FPGA
  31  * test code of sun50iw3 platform.
  32  */
  33 struct sunxi_mctl_com_reg {
  34         u32 cr;                 /* 0x000 control register */
  35         u8 reserved_0x004[4];   /* 0x004 */
  36         u32 unk_0x008;          /* 0x008 */
  37         u32 tmr;                /* 0x00c timer register */
  38         u8 reserved_0x010[4];   /* 0x010 */
  39         u32 unk_0x014;          /* 0x014 */
  40         u8 reserved_0x018[8];   /* 0x018 */
  41         u32 maer0;              /* 0x020 master enable register 0 */
  42         u32 maer1;              /* 0x024 master enable register 1 */
  43         u32 maer2;              /* 0x028 master enable register 2 */
  44         u8 reserved_0x02c[468]; /* 0x02c */
  45         u32 bwcr;               /* 0x200 bandwidth control register */
  46         u8 reserved_0x204[12];  /* 0x204 */
  47         /*
  48          * The last master configured by BSP libdram is at 0x49x, so the
  49          * size of this struct array is set to 41 (0x29) now.
  50          */
  51         struct {
  52                 u32 cfg0;               /* 0x0 */
  53                 u32 cfg1;               /* 0x4 */
  54                 u8 reserved_0x8[8];     /* 0x8 */
  55         } master[41];           /* 0x210 + index * 0x10 */
  56 };
  57 check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498);
  58
  59 /*
  60  * The following register information are retrieved from some similar DRAM
  61  * controllers, including the DRAM controllers in Allwinner A23/A80 SoCs,
  62  * Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs.
  63  *
  64  * The DRAM controller in Allwinner A23/A80 SoCs and NXP i.MX7 SoCs seems
  65  * to be older than the one in Allwinner H6, as the DRAMTMG9 register
  66  * is missing in these SoCs. (From the product specifications of these
  67  * SoCs they're not capable of DDR4)
  68  *
  69  * Information sources:
  70  * - dram_sun9i.h and dram_sun8i_a23.h in the same directory.
  71  * - sdram_rk3328.h from the RK3328 TPL DRAM patchset
  72  * - i.MX 7Solo Applications Processor Reference Manual (IMX7SRM)
  73  * - Zynq UltraScale+ MPSoC Register Reference (UG1087)
  74  */
  75 struct sunxi_mctl_ctl_reg {
  76         u32 mstr;               /* 0x000 */
  77         u32 statr;              /* 0x004 unused */
  78         u32 mstr1;              /* 0x008 unused */
  79         u32 unk_0x00c;          /* 0x00c */
  80         u32 mrctrl0;            /* 0x010 unused */
  81         u32 mrctrl1;            /* 0x014 unused */
  82         u32 mrstatr;            /* 0x018 unused */
  83         u32 mrctrl2;            /* 0x01c unused */
  84         u32 derateen;           /* 0x020 unused */
  85         u32 derateint;          /* 0x024 unused */
  86         u8 reserved_0x028[8];   /* 0x028 */
  87         u32 pwrctl;             /* 0x030 unused */
  88         u32 pwrtmg;             /* 0x034 unused */
  89         u32 hwlpctl;            /* 0x038 unused */
  90         u8 reserved_0x03c[20];  /* 0x03c */
  91         u32 rfshctl0;           /* 0x050 unused */
  92         u32 rfshctl1;           /* 0x054 unused */
  93         u8 reserved_0x058[8];   /* 0x05c */
  94         u32 rfshctl3;           /* 0x060 */
  95         u32 rfshtmg;            /* 0x064 */
  96         u8 reserved_0x068[104]; /* 0x068 reserved for ECC&CRC (from ZynqMP) */
  97         u32 init[8];            /* 0x0d0 */
  98         u32 dimmctl;            /* 0x0f0 unused */
  99         u32 rankctl;            /* 0x0f4 */
 100         u8 reserved_0x0f8[8];   /* 0x0f8 */
 101         u32 dramtmg[17];        /* 0x100 */
 102         u8 reserved_0x144[60];  /* 0x144 */
 103         u32 zqctl[3];           /* 0x180 */
 104         u32 zqstat;             /* 0x18c unused */
 105         u32 dfitmg0;            /* 0x190 */
 106         u32 dfitmg1;            /* 0x194 */
 107         u32 dfilpcfg[2];        /* 0x198 unused */
 108         u32 dfiupd[3];          /* 0x1a0 */
 109         u32 reserved_0x1ac;     /* 0x1ac */
 110         u32 dfimisc;            /* 0x1b0 */
 111         u32 dfitmg2;            /* 0x1b4 unused, may not exist */
 112         u8 reserved_0x1b8[8];   /* 0x1b8 */
 113         u32 dbictl;             /* 0x1c0 */
 114         u8 reserved_0x1c4[60];  /* 0x1c4 */
 115         u32 addrmap[12];        /* 0x200 */
 116         u8 reserved_0x230[16];  /* 0x230 */
 117         u32 odtcfg;             /* 0x240 */
 118         u32 odtmap;             /* 0x244 */
 119         u8 reserved_0x248[8];   /* 0x248 */
 120         u32 sched[2];           /* 0x250 */
 121         u8 reserved_0x258[180]; /* 0x258 */
 122         u32 dbgcmd;             /* 0x30c unused */
 123         u32 dbgstat;            /* 0x310 unused */
 124         u8 reserved_0x314[12];  /* 0x314 */
 125         u32 swctl;              /* 0x320 */
 126         u32 swstat;             /* 0x324 */
 127 };
 128 check_member(sunxi_mctl_ctl_reg, swstat, 0x324);
 129
 130 #define MSTR_DEVICETYPE_DDR3    BIT(0)
 131 #define MSTR_DEVICETYPE_LPDDR2  BIT(2)
 132 #define MSTR_DEVICETYPE_LPDDR3  BIT(3)
 133 #define MSTR_DEVICETYPE_DDR4    BIT(4)
 134 #define MSTR_DEVICETYPE_MASK    GENMASK(5, 0)
 135 #define MSTR_2TMODE             BIT(10)
 136 #define MSTR_BUSWIDTH_FULL      (0 << 12)
 137 #define MSTR_BUSWIDTH_HALF      (1 << 12)
 138 #define MSTR_ACTIVE_RANKS(x)    (((x == 2) ? 3 : 1) << 24)
 139 #define MSTR_BURST_LENGTH(x)    (((x) >> 1) << 16)
 140
 141 /*
 142  * The following register information is based on Zynq UltraScale+
 143  * MPSoC Register Reference, as it's the currently only known
 144  * DDR PHY similar to the one used in H6; however although the
 145  * map is similar, the bit fields definitions are different.
 146  *
 147  * Other DesignWare DDR PHY's have similar register names, but the
 148  * offset and definitions are both different.
 149  */
 150 struct sunxi_mctl_phy_reg {
 151         u32 ver;                /* 0x000 guess based on similar PHYs */
 152         u32 pir;                /* 0x004 */
 153         u8 reserved_0x008[8];   /* 0x008 */
 154         /*
 155          * The ZynqMP manual didn't document PGCR1, however this register
 156          * exists on H6 and referenced by libdram.
 157          */
 158         u32 pgcr[8];            /* 0x010 */
 159         /*
 160          * By comparing the hardware and the ZynqMP manual, the PGSR seems
 161          * to start at 0x34 on H6.
 162          */
 163         u8 reserved_0x030[4];   /* 0x030 */
 164         u32 pgsr[3];            /* 0x034 */
 165         u32 ptr[7];             /* 0x040 */
 166         /*
 167          * According to ZynqMP reference there's PLLCR0~6 in this area,
 168          * but they're tagged "Type B PLL Only" and H6 seems to have
 169          * no them.
 170          * 0x080 is not present in ZynqMP reference but it seems to be
 171          * present on H6.
 172          */
 173         u8 reserved_0x05c[36];  /* 0x05c */
 174         u32 unk_0x080;          /* 0x080 */
 175         u8 reserved_0x084[4];   /* 0x084 */
 176         u32 dxccr;              /* 0x088 */
 177         u8 reserved_0x08c[4];   /* 0x08c */
 178         u32 dsgcr;              /* 0x090 */
 179         u8 reserved_0x094[4];   /* 0x094 */
 180         u32 odtcr;              /* 0x098 */
 181         u8 reserved_0x09c[4];   /* 0x09c */
 182         u32 aacr;               /* 0x0a0 */
 183         u8 reserved_0x0a4[32];  /* 0x0a4 */
 184         u32 gpr1;               /* 0x0c4 */
 185         u8 reserved_0x0c8[56];  /* 0x0c8 */
 186         u32 dcr;                /* 0x100 */
 187         u8 reserved_0x104[12];  /* 0x104 */
 188         u32 dtpr[7];            /* 0x110 */
 189         u8 reserved_0x12c[20];  /* 0x12c */
 190         u32 rdimmgcr[3];        /* 0x140 */
 191         u8 reserved_0x14c[4];   /* 0x14c */
 192         u32 rdimmcr[5];         /* 0x150 */
 193         u8 reserved_0x164[4];   /* 0x164 */
 194         u32 schcr[2];           /* 0x168 */
 195         u8 reserved_0x170[16];  /* 0x170 */
 196         /*
 197          * The ZynqMP manual documents MR0~7, 11~14 and 22.
 198          */
 199         u32 mr[23];             /* 0x180 */
 200         u8 reserved_0x1dc[36];  /* 0x1dc */
 201         u32 dtcr[2];            /* 0x200 */
 202         u32 dtar[3];            /* 0x208 */
 203         u8 reserved_0x214[4];   /* 0x214 */
 204         u32 dtdr[2];            /* 0x218 */
 205         u8 reserved_0x220[16];  /* 0x220 */
 206         u32 dtedr0;             /* 0x230 */
 207         u32 dtedr1;             /* 0x234 */
 208         u32 dtedr2;             /* 0x238 */
 209         u32 vtdr;               /* 0x23c */
 210         u32 catr[2];            /* 0x240 */
 211         u8 reserved_0x248[8];
 212         u32 dqsdr[3];           /* 0x250 */
 213         u32 dtedr3;             /* 0x25c */
 214         u8 reserved_0x260[160]; /* 0x260 */
 215         u32 dcuar;              /* 0x300 */
 216         u32 dcudr;              /* 0x304 */
 217         u32 dcurr;              /* 0x308 */
 218         u32 dculr;              /* 0x30c */
 219         u32 dcugcr;             /* 0x310 */
 220         u32 dcutpr;             /* 0x314 */
 221         u32 dcusr[2];           /* 0x318 */
 222         u8 reserved_0x320[444]; /* 0x320 */
 223         u32 rankidr;            /* 0x4dc */
 224         u32 riocr[6];           /* 0x4e0 */
 225         u8 reserved_0x4f8[8];   /* 0x4f8 */
 226         u32 aciocr[6];          /* 0x500 */
 227         u8 reserved_0x518[8];   /* 0x518 */
 228         u32 iovcr[2];           /* 0x520 */
 229         u32 vtcr[2];            /* 0x528 */
 230         u8 reserved_0x530[16];  /* 0x530 */
 231         u32 acbdlr[17];         /* 0x540 */
 232         u32 aclcdlr;            /* 0x584 */
 233         u8 reserved_0x588[24];  /* 0x588 */
 234         u32 acmdlr[2];          /* 0x5a0 */
 235         u8 reserved_0x5a8[216]; /* 0x5a8 */
 236         struct {
 237                 u32 zqcr;       /* 0x00 only the first one valid */
 238                 u32 zqpr[2];    /* 0x04 */
 239                 u32 zqdr[2];    /* 0x0c */
 240                 u32 zqor[2];    /* 0x14 */
 241                 u32 zqsr;       /* 0x1c */
 242         } zq[2];                /* 0x680, 0x6a0 */
 243         u8 reserved_0x6c0[64];  /* 0x6c0 */
 244         struct {
 245                 u32 gcr[7];             /* 0x00 */
 246                 u8 reserved_0x1c[36];   /* 0x1c */
 247                 u32 bdlr0;              /* 0x40 */
 248                 u32 bdlr1;              /* 0x44 */
 249                 u32 bdlr2;              /* 0x48 */
 250                 u8 reserved_0x4c[4];    /* 0x4c */
 251                 u32 bdlr3;              /* 0x50 */
 252                 u32 bdlr4;              /* 0x54 */
 253                 u32 bdlr5;              /* 0x58 */
 254                 u8 reserved_0x5c[4];    /* 0x5c */
 255                 u32 bdlr6;              /* 0x60 */
 256                 u8 reserved_0x64[28];   /* 0x64 */
 257                 u32 lcdlr[6];           /* 0x80 */
 258                 u8 reserved_0x98[8];    /* 0x98 */
 259                 u32 mdlr[2];            /* 0xa0 */
 260                 u8 reserved_0xa8[24];   /* 0xa8 */
 261                 u32 gtr0;               /* 0xc0 */
 262                 u8 reserved_0xc4[12];   /* 0xc4 */
 263                 /*
 264                  * DXnRSR0 is not documented in ZynqMP manual but
 265                  * it's used in libdram.
 266                  */
 267                 u32 rsr[4];             /* 0xd0 */
 268                 u32 gsr[4];             /* 0xe0 */
 269                 u8 reserved_0xf0[16];   /* 0xf0 */
 270         } dx[4];                /* 0x700, 0x800, 0x900, 0xa00 */
 271 };
 272 check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0);
 273
 274 #define PIR_INIT        BIT(0)
 275 #define PIR_ZCAL        BIT(1)
 276 #define PIR_CA          BIT(2)
 277 #define PIR_PLLINIT     BIT(4)
 278 #define PIR_DCAL        BIT(5)
 279 #define PIR_PHYRST      BIT(6)
 280 #define PIR_DRAMRST     BIT(7)
 281 #define PIR_DRAMINIT    BIT(8)
 282 #define PIR_WL          BIT(9)
 283 #define PIR_QSGATE      BIT(10)
 284 #define PIR_WLADJ       BIT(11)
 285 #define PIR_RDDSKW      BIT(12)
 286 #define PIR_WRDSKW      BIT(13)
 287 #define PIR_RDEYE       BIT(14)
 288 #define PIR_WREYE       BIT(15)
 289 #define PIR_VREF        BIT(17)
 290 #define PIR_CTLDINIT    BIT(18)
 291 #define PIR_DQS2DQ      BIT(20)
 292 #define PIR_DCALPSE     BIT(29)
 293 #define PIR_ZCALBYP     BIT(30)
 294
 295 #define DCR_LPDDR3      (1 << 0)
 296 #define DCR_DDR3        (3 << 0)
 297 #define DCR_DDR4        (4 << 0)
 298 #define DCR_DDR8BANK    BIT(3)
 299 #define DCR_DDR2T       BIT(28)
 300
 301 /*
 302  * The delay parameters allow to allegedly specify delay times of some
 303  * unknown unit for each individual bit trace in each of the four data bytes
 304  * the 32-bit wide access consists of. Also three control signals can be
 305  * adjusted individually.
 306  */
 307 #define NR_OF_BYTE_LANES        (32 / BITS_PER_BYTE)
 308 /* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */
 309 #define WR_LINES_PER_BYTE_LANE  (BITS_PER_BYTE + 4)
 310 /*
 311  * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN,
 312  * Termination and Power down
 313  */
 314 #define RD_LINES_PER_BYTE_LANE  (BITS_PER_BYTE + 6)
 315 struct dram_para {
 316         u32 clk;
 317         enum sunxi_dram_type type;
 318         u8 cols;
 319         u8 rows;
 320         u8 ranks;
 321         u8 bus_full_width;
 322         const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
 323         const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
 324 };
 325
 326
 327 static inline int ns_to_t(int nanoseconds)
 328 {
 329         const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
 330
 331         return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
 332 }
 333
 334 void mctl_set_timing_params(struct dram_para *para);
 335
 336 #endif /* _SUNXI_DRAM_SUN50I_H6_H */