1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Rockchip Inc.
6 #ifndef _ASM_ARCH_LVDS_RK3288_H
7 #define _ASM_ARCH_LVDS_RK3288_H
10 #include <linux/bitops.h>
13 #define RK3288_LVDS_CH0_REG0 0x00
14 #define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7)
15 #define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6)
16 #define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5)
17 #define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4)
18 #define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3)
19 #define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2)
20 #define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1)
21 #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)
23 #define RK3288_LVDS_CH0_REG1 0x04
24 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5)
25 #define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4)
26 #define RK3288_LVDS_CH0_REG1_LANE3_BIAS BIT(3)
27 #define RK3288_LVDS_CH0_REG1_LANE2_BIAS BIT(2)
28 #define RK3288_LVDS_CH0_REG1_LANE1_BIAS BIT(1)
29 #define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0)
31 #define RK3288_LVDS_CH0_REG2 0x08
32 #define RK3288_LVDS_CH0_REG2_RESERVE_ON BIT(7)
33 #define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE BIT(6)
34 #define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE BIT(5)
35 #define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE BIT(4)
36 #define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE BIT(3)
37 #define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE BIT(2)
38 #define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE BIT(1)
39 #define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0)
41 #define RK3288_LVDS_CH0_REG3 0x0c
42 #define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK 0xff
44 #define RK3288_LVDS_CH0_REG4 0x10
45 #define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE BIT(5)
46 #define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE BIT(4)
47 #define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE BIT(3)
48 #define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE BIT(2)
49 #define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE BIT(1)
50 #define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0)
52 #define RK3288_LVDS_CH0_REG5 0x14
53 #define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA BIT(5)
54 #define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA BIT(4)
55 #define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA BIT(3)
56 #define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA BIT(2)
57 #define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA BIT(1)
58 #define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0)
60 #define RK3288_LVDS_CFG_REGC 0x30
61 #define RK3288_LVDS_CFG_REGC_PLL_ENABLE 0x00
62 #define RK3288_LVDS_CFG_REGC_PLL_DISABLE 0xff
64 #define RK3288_LVDS_CH0_REGD 0x34
65 #define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK 0x1f
67 #define RK3288_LVDS_CH0_REG20 0x80
68 #define RK3288_LVDS_CH0_REG20_MSB 0x45
69 #define RK3288_LVDS_CH0_REG20_LSB 0x44
71 #define RK3288_LVDS_CFG_REG21 0x84
72 #define RK3288_LVDS_CFG_REG21_TX_ENABLE 0x92
73 #define RK3288_LVDS_CFG_REG21_TX_DISABLE 0x00
75 /* fbdiv value is split over 2 registers, with bit8 in reg2 */
76 #define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \
77 (_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
78 #define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \
79 (_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK)
80 #define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \
81 (_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK)
83 #define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT BIT(3)
85 #define LVDS_FMT_MASK (7 << 16)
86 #define LVDS_MSB (1 << 3)
87 #define LVDS_DUAL (1 << 4)
88 #define LVDS_FMT_1 (1 << 5)
89 #define LVDS_TTL_EN (1 << 6)
90 #define LVDS_START_PHASE_RST_1 (1 << 7)
91 #define LVDS_DCLK_INV (1 << 8)
92 #define LVDS_CH0_EN (1 << 11)
93 #define LVDS_CH1_EN (1 << 12)
94 #define LVDS_PWRDN (1 << 15)
96 #define LVDS_24BIT (0 << 1)
97 #define LVDS_18BIT (1 << 1)