1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
6 #ifndef __ASM_ARCH_CRU_RK3328_H_
7 #define __ASM_ARCH_CRU_RK3328_H_
9 struct rk3328_clk_priv {
10 struct rk3328_cru *cru;
28 u32 glb_srst_snd_value;
29 u32 glb_srst_fst_value;
31 u32 reserved6[(0x100 - 0xb4) / 4];
33 u32 reserved7[(0x200 - 0x1d4) / 4];
38 u32 reserved9[(0x380 - 0x330) / 4];
44 check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
47 #define OSC_HZ (24 * MHz)
48 #define APLL_HZ (600 * MHz)
49 #define GPLL_HZ (576 * MHz)
50 #define CPLL_HZ (594 * MHz)
52 #define CLK_CORE_HZ (600 * MHz)
53 #define ACLKM_CORE_HZ (300 * MHz)
54 #define PCLK_DBG_HZ (300 * MHz)
56 #define PERIHP_ACLK_HZ (144000 * KHz)
57 #define PERIHP_HCLK_HZ (72000 * KHz)
58 #define PERIHP_PCLK_HZ (72000 * KHz)
60 #define PWM_CLOCK_HZ (74 * MHz)
62 enum apll_frequencies {
67 void rk3328_configure_cpu(struct rk3328_cru *cru,
68 enum apll_frequencies apll_freq);
70 #endif /* __ASM_ARCH_CRU_RK3328_H_ */