1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
6 * Peng Fan <Peng.Fan@freescale.com>
9 #ifndef _ASM_ARCH_CLOCK_H
10 #define _ASM_ARCH_CLOCK_H
12 #include <asm/arch/crm_regs.h>
14 #ifdef CONFIG_SYS_MX7_HCLK
15 #define MXC_HCLK CONFIG_SYS_MX7_HCLK
17 #define MXC_HCLK 24000000
20 #ifdef CONFIG_SYS_MX7_CLK32
21 #define MXC_CLK32 CONFIG_SYS_MX7_CLK32
23 #define MXC_CLK32 32768
26 /* Mainly for compatible to imx common code. */
41 /* PLL supported by i.mx7d */
43 PLL_CORE, /* Core PLL */
44 PLL_SYS, /* System PLL*/
45 PLL_ENET, /* Enet PLL */
46 PLL_AUDIO, /* Audio PLL */
47 PLL_VIDEO, /* Video PLL*/
48 PLL_DDR, /* Dram PLL */
49 PLL_USB, /* USB PLL, fixed at 480MHZ */
52 /* clk src for clock root gen */
56 PLL_ARM_MAIN_800M_CLK,
58 PLL_SYS_MAIN_480M_CLK,
59 PLL_SYS_MAIN_240M_CLK,
60 PLL_SYS_MAIN_120M_CLK,
61 PLL_SYS_PFD0_392M_CLK,
62 PLL_SYS_PFD0_196M_CLK,
63 PLL_SYS_PFD1_332M_CLK,
64 PLL_SYS_PFD1_166M_CLK,
65 PLL_SYS_PFD2_270M_CLK,
66 PLL_SYS_PFD2_135M_CLK,
73 PLL_ENET_MAIN_500M_CLK,
74 PLL_ENET_MAIN_250M_CLK,
75 PLL_ENET_MAIN_125M_CLK,
76 PLL_ENET_MAIN_100M_CLK,
77 PLL_ENET_MAIN_50M_CLK,
78 PLL_ENET_MAIN_40M_CLK,
79 PLL_ENET_MAIN_25M_CLK,
81 PLL_DRAM_MAIN_1066M_CLK,
82 PLL_DRAM_MAIN_533M_CLK,
87 PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */
101 enum clk_root_index {
105 MAIN_AXI_CLK_ROOT = 16,
106 DISP_AXI_CLK_ROOT = 17,
107 ENET_AXI_CLK_ROOT = 18,
108 NAND_USDHC_BUS_CLK_ROOT = 19,
110 DRAM_PHYM_CLK_ROOT = 48,
112 DRAM_PHYM_ALT_CLK_ROOT = 64,
113 DRAM_ALT_CLK_ROOT = 65,
114 USB_HSIC_CLK_ROOT = 66,
115 PCIE_CTRL_CLK_ROOT = 67,
116 PCIE_PHY_CLK_ROOT = 68,
117 EPDC_PIXEL_CLK_ROOT = 69,
118 LCDIF_PIXEL_CLK_ROOT = 70,
119 MIPI_DSI_EXTSER_CLK_ROOT = 71,
120 MIPI_CSI_WARP_CLK_ROOT = 72,
121 MIPI_DPHY_REF_CLK_ROOT = 73,
126 ENET1_REF_CLK_ROOT = 78,
127 ENET1_TIME_CLK_ROOT = 79,
128 ENET2_REF_CLK_ROOT = 80,
129 ENET2_TIME_CLK_ROOT = 81,
130 ENET_PHY_REF_CLK_ROOT = 82,
134 USDHC1_CLK_ROOT = 86,
135 USDHC2_CLK_ROOT = 87,
136 USDHC3_CLK_ROOT = 88,
148 UART6_CLK_ROOT = 100,
149 UART7_CLK_ROOT = 101,
150 ECSPI1_CLK_ROOT = 102,
151 ECSPI2_CLK_ROOT = 103,
152 ECSPI3_CLK_ROOT = 104,
153 ECSPI4_CLK_ROOT = 105,
158 FLEXTIMER1_CLK_ROOT = 110,
159 FLEXTIMER2_CLK_ROOT = 111,
166 TRACE_CLK_ROOT = 118,
168 CSI_MCLK_CLK_ROOT = 120,
169 AUDIO_MCLK_CLK_ROOT = 121,
170 WRCLK_CLK_ROOT = 122,
177 #if (CONFIG_CONS_INDEX == 0)
178 #define UART_CLK_ROOT UART1_CLK_ROOT
179 #elif (CONFIG_CONS_INDEX == 1)
180 #define UART_CLK_ROOT UART2_CLK_ROOT
181 #elif (CONFIG_CONS_INDEX == 2)
182 #define UART_CLK_ROOT UART3_CLK_ROOT
183 #elif (CONFIG_CONS_INDEX == 3)
184 #define UART_CLK_ROOT UART4_CLK_ROOT
185 #elif (CONFIG_CONS_INDEX == 4)
186 #define UART_CLK_ROOT UART5_CLK_ROOT
187 #elif (CONFIG_CONS_INDEX == 5)
188 #define UART_CLK_ROOT UART6_CLK_ROOT
189 #elif (CONFIG_CONS_INDEX == 6)
190 #define UART_CLK_ROOT UART7_CLK_ROOT
192 #error "Invalid IMX UART ID for serial console is defined"
195 struct clk_root_setting {
196 enum clk_root_index root;
203 enum clk_ccgr_index {
207 CCGR_SIM_DISPLAY = 5,
233 CCGR_QOS_DISPMIX = 43,
234 CCGR_QOS_MEGAMIX = 44,
252 CCGR_MIPI_MEM_PHY = 102,
306 CCGR_IOMUX_LPSR = 169,
313 /* Clock root channel */
318 CCM_DRAM_PHYM_CHANNEL,
323 #include <asm/arch/clock_slice.h>
326 * entry: the clock root index
328 * src_mux: each entry corresponding to the clock src, detailed info in CCM RM
330 struct clk_root_map {
331 enum clk_root_index entry;
332 enum clk_root_type type;
342 u32 get_root_clk(enum clk_root_index clock_id);
343 u32 mxc_get_clock(enum mxc_clock clk);
344 u32 imx_get_uartclk(void);
345 u32 imx_get_fecclk(void);
346 void clock_init(void);
347 #ifdef CONFIG_SYS_I2C_MXC
348 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
350 #ifdef CONFIG_FEC_MXC
351 int set_clk_enet(enum enet_freq type);
353 int set_clk_qspi(void);
354 int set_clk_nand(void);
355 #ifdef CONFIG_MXC_OCOTP
356 void enable_ocotp_clk(unsigned char enable);
358 void enable_usboh3_clk(unsigned char enable);
359 #ifdef CONFIG_IMX_HAB
360 void hab_caam_clock_enable(unsigned char enable);
362 void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
363 void enable_thermal_clk(void);