arch/arm/dts/zynqmp-zcu216-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU216
   4  *
   5  * (C) Copyright 2017 - 2020, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU216 RevA";
  20         compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &dcc;
  31                 spi0 = &qspi;
  32                 usb0 = &usb0;
  33         };
  34
  35         chosen {
  36                 bootargs = "earlycon";
  37                 stdout-path = "serial0:115200n8";
  38                 xlnx,eeprom = <&eeprom>;
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48                 autorepeat;
  49                 sw19 {
  50                         label = "sw19";
  51                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  52                         linux,code = <KEY_DOWN>;
  53                         wakeup-source;
  54                         autorepeat;
  55                 };
  56         };
  57
  58         leds {
  59                 compatible = "gpio-leds";
  60                 heartbeat_led {
  61                         label = "heartbeat";
  62                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  63                         linux,default-trigger = "heartbeat";
  64                 };
  65         };
  66
  67         ina226-vccint {
  68                 compatible = "iio-hwmon";
  69                 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
  70         };
  71         ina226-vccint-io-bram-ps {
  72                 compatible = "iio-hwmon";
  73                 io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
  74         };
  75         ina226-vcc1v8 {
  76                 compatible = "iio-hwmon";
  77                 io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
  78         };
  79         ina226-vcc1v2 {
  80                 compatible = "iio-hwmon";
  81                 io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
  82         };
  83         ina226-vadj-fmc {
  84                 compatible = "iio-hwmon";
  85                 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
  86         };
  87         ina226-mgtavcc {
  88                 compatible = "iio-hwmon";
  89                 io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
  90         };
  91         ina226-mgt1v2 {
  92                 compatible = "iio-hwmon";
  93                 io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
  94         };
  95         ina226-mgt1v8 {
  96                 compatible = "iio-hwmon";
  97                 io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
  98         };
  99         ina226-vccint-ams {
 100                 compatible = "iio-hwmon";
 101                 io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
 102         };
 103         ina226-dac-avtt {
 104                 compatible = "iio-hwmon";
 105                 io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
 106         };
 107         ina226-dac-avccaux {
 108                 compatible = "iio-hwmon";
 109                 io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
 110         };
 111         ina226-adc-avcc {
 112                 compatible = "iio-hwmon";
 113                 io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
 114         };
 115         ina226-adc-avccaux {
 116                 compatible = "iio-hwmon";
 117                 io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
 118         };
 119         ina226-dac-avcc {
 120                 compatible = "iio-hwmon";
 121                 io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
 122         };
 123 };
 124
 125 &dcc {
 126         status = "okay";
 127 };
 128
 129 &fpd_dma_chan1 {
 130         status = "okay";
 131 };
 132
 133 &fpd_dma_chan2 {
 134         status = "okay";
 135 };
 136
 137 &fpd_dma_chan3 {
 138         status = "okay";
 139 };
 140
 141 &fpd_dma_chan4 {
 142         status = "okay";
 143 };
 144
 145 &fpd_dma_chan5 {
 146         status = "okay";
 147 };
 148
 149 &fpd_dma_chan6 {
 150         status = "okay";
 151 };
 152
 153 &fpd_dma_chan7 {
 154         status = "okay";
 155 };
 156
 157 &fpd_dma_chan8 {
 158         status = "okay";
 159 };
 160
 161 &gem3 {
 162         status = "okay";
 163         phy-handle = <&phy0>;
 164         phy-mode = "rgmii-id";
 165         phy0: ethernet-phy@c {
 166                 reg = <0xc>;
 167                 ti,rx-internal-delay = <0x8>;
 168                 ti,tx-internal-delay = <0xa>;
 169                 ti,fifo-depth = <0x1>;
 170                 ti,dp83867-rxctrl-strap-quirk;
 171         };
 172 };
 173
 174 &gpio {
 175         status = "okay";
 176         gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
 177                   "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
 178                   "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
 179                   "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
 180                   "", "", "BUTTON", "LED", "", /* 20 - 24 */
 181                   "", "PMU_INPUT", "", "", "", /* 25 - 29 */
 182                   "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
 183                   "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
 184                   "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
 185                   "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
 186                   "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
 187                   "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
 188                   "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
 189                   "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
 190                   "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
 191                   "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
 192                   "", "", /* 78 - 79 */
 193                   "", "", "", "", "", /* 80 - 84 */
 194                   "", "", "", "", "", /* 85 -89 */
 195                   "", "", "", "", "", /* 90 - 94 */
 196                   "", "", "", "", "", /* 95 - 99 */
 197                   "", "", "", "", "", /* 100 - 104 */
 198                   "", "", "", "", "", /* 105 - 109 */
 199                   "", "", "", "", "", /* 110 - 114 */
 200                   "", "", "", "", "", /* 115 - 119 */
 201                   "", "", "", "", "", /* 120 - 124 */
 202                   "", "", "", "", "", /* 125 - 129 */
 203                   "", "", "", "", "", /* 130 - 134 */
 204                   "", "", "", "", "", /* 135 - 139 */
 205                   "", "", "", "", "", /* 140 - 144 */
 206                   "", "", "", "", "", /* 145 - 149 */
 207                   "", "", "", "", "", /* 150 - 154 */
 208                   "", "", "", "", "", /* 155 - 159 */
 209                   "", "", "", "", "", /* 160 - 164 */
 210                   "", "", "", "", "", /* 165 - 169 */
 211                   "", "", "", ""; /* 170 - 174 */
 212 };
 213
 214 &gpu {
 215         status = "okay";
 216 };
 217
 218 &i2c0 {
 219         status = "okay";
 220         clock-frequency = <400000>;
 221
 222         tca6416_u15: gpio@20 { /* u15 */
 223                 compatible = "ti,tca6416";
 224                 reg = <0x20>;
 225                 gpio-controller; /* interrupt not connected */
 226                 #gpio-cells = <2>;
 227                 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */
 228                                   "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
 229                                   "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
 230                                   "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
 231         };
 232
 233         i2c-mux@75 { /* u17 */
 234                 compatible = "nxp,pca9544";
 235                 #address-cells = <1>;
 236                 #size-cells = <0>;
 237                 reg = <0x75>;
 238                 i2c@0 {
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                         reg = <0>;
 242                         /* PS_PMBUS */
 243                         /* PMBUS_ALERT done via pca9544 */
 244                         vccint: ina226@40 { /* u65 */
 245                                 compatible = "ti,ina226";
 246                                 #io-channel-cells = <1>;
 247                                 label = "ina226-vccint";
 248                                 reg = <0x40>;
 249                                 shunt-resistor = <5000>;
 250                         };
 251                         vccint_io_bram_ps: ina226@41 { /* u57 */
 252                                 compatible = "ti,ina226";
 253                                 #io-channel-cells = <1>;
 254                                 label = "ina226-vccint-io-bram-ps";
 255                                 reg = <0x41>;
 256                                 shunt-resistor = <5000>;
 257                         };
 258                         vcc1v8: ina226@42 { /* u60 */
 259                                 compatible = "ti,ina226";
 260                                 #io-channel-cells = <1>;
 261                                 label = "ina226-vcc1v8";
 262                                 reg = <0x42>;
 263                                 shunt-resistor = <2000>;
 264                         };
 265                         vcc1v2: ina226@43 { /* u58 */
 266                                 compatible = "ti,ina226";
 267                                 #io-channel-cells = <1>;
 268                                 label = "ina226-vcc1v2";
 269                                 reg = <0x43>;
 270                                 shunt-resistor = <5000>;
 271                         };
 272                         vadj_fmc: ina226@45 { /* u62 */
 273                                 compatible = "ti,ina226";
 274                                 #io-channel-cells = <1>;
 275                                 label = "ina226-vadj-fmc";
 276                                 reg = <0x45>;
 277                                 shunt-resistor = <5000>;
 278                         };
 279                         mgtavcc: ina226@46 { /* u67 */
 280                                 compatible = "ti,ina226";
 281                                 #io-channel-cells = <1>;
 282                                 label = "ina226-mgtavcc";
 283                                 reg = <0x46>;
 284                                 shunt-resistor = <2000>;
 285                         };
 286                         mgt1v2: ina226@47 { /* u63 */
 287                                 compatible = "ti,ina226";
 288                                 #io-channel-cells = <1>;
 289                                 label = "ina226-mgt1v2";
 290                                 reg = <0x47>;
 291                                 shunt-resistor = <5000>;
 292                         };
 293                         mgt1v8: ina226@48 { /* u64 */
 294                                 compatible = "ti,ina226";
 295                                 #io-channel-cells = <1>;
 296                                 label = "ina226-mgt1v8";
 297                                 reg = <0x48>;
 298                                 shunt-resistor = <5000>;
 299                         };
 300                         vccint_ams: ina226@49 { /* u61 */
 301                                 compatible = "ti,ina226";
 302                                 #io-channel-cells = <1>;
 303                                 label = "ina226-vccint-ams";
 304                                 reg = <0x49>;
 305                                 shunt-resistor = <5000>;
 306                         };
 307                         dac_avtt: ina226@4a { /* u59 */
 308                                 compatible = "ti,ina226";
 309                                 #io-channel-cells = <1>;
 310                                 label = "ina226-dac-avtt";
 311                                 reg = <0x4a>;
 312                                 shunt-resistor = <5000>;
 313                         };
 314                         dac_avccaux: ina226@4b { /* u124 */
 315                                 compatible = "ti,ina226";
 316                                 #io-channel-cells = <1>;
 317                                 label = "ina226-dac-avccaux";
 318                                 reg = <0x4b>;
 319                                 shunt-resistor = <5000>;
 320                         };
 321                         adc_avcc: ina226@4c { /* u75 */
 322                                 compatible = "ti,ina226";
 323                                 #io-channel-cells = <1>;
 324                                 label = "ina226-adc-avcc";
 325                                 reg = <0x4c>;
 326                                 shunt-resistor = <5000>;
 327                         };
 328                         adc_avccaux: ina226@4d { /* u71 */
 329                                 compatible = "ti,ina226";
 330                                 #io-channel-cells = <1>;
 331                                 label = "ina226-adc-avccaux";
 332                                 reg = <0x4d>;
 333                                 shunt-resistor = <5000>;
 334                         };
 335                         dac_avcc: ina226@4e { /* u77 */
 336                                 compatible = "ti,ina226";
 337                                 #io-channel-cells = <1>;
 338                                 label = "ina226-dac-avcc";
 339                                 reg = <0x4e>;
 340                                 shunt-resistor = <5000>;
 341                         };
 342                 };
 343                 i2c@1 {
 344                         #address-cells = <1>;
 345                         #size-cells = <0>;
 346                         reg = <1>;
 347                         /* NC */
 348                 };
 349                 i2c@2 {
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         reg = <2>;
 353                         /* u104 - ir35215 0x10/0x40 */
 354                         /* u127 - ir38164 0x1b/0x4b */
 355                         /* u112 - ir38164 0x13/0x43 */
 356                         /* u123 - ir38164 0x1c/0x4c */
 357
 358                         irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
 359                                 compatible = "infineon,irps5401";
 360                                 reg = <0x44>; /* i2c addr 0x14 */
 361                         };
 362                         irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
 363                                 compatible = "infineon,irps5401";
 364                                 reg = <0x45>; /* i2c addr 0x15 */
 365                         };
 366                         /* J21 header too */
 367
 368                 };
 369                 i2c@3 {
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         reg = <3>;
 373                         /* SYSMON */
 374                 };
 375         };
 376         /* u38 MPS430 */
 377 };
 378
 379 &i2c1 {
 380         status = "okay";
 381         clock-frequency = <400000>;
 382
 383         i2c-mux@74 {
 384                 compatible = "nxp,pca9548"; /* u20 */
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 reg = <0x74>;
 388                 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
 389                 i2c_eeprom: i2c@0 {
 390                         #address-cells = <1>;
 391                         #size-cells = <0>;
 392                         reg = <0>;
 393                         /*
 394                          * IIC_EEPROM 1kB memory which uses 256B blocks
 395                          * where every block has different address.
 396                          *    0 - 256B address 0x54
 397                          * 256B - 512B address 0x55
 398                          * 512B - 768B address 0x56
 399                          * 768B - 1024B address 0x57
 400                          */
 401                         eeprom: eeprom@54 { /* u21 */
 402                                 compatible = "atmel,24c128";
 403                                 reg = <0x54>;
 404                         };
 405                 };
 406                 i2c_si5341: i2c@1 {
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409                         reg = <1>;
 410                         si5341: clock-generator@36 { /* SI5341 - u43 */
 411                                 compatible = "si5341";
 412                                 reg = <0x36>;
 413                         };
 414
 415                 };
 416                 i2c_si570_user_c0: i2c@2 {
 417                         #address-cells = <1>;
 418                         #size-cells = <0>;
 419                         reg = <2>;
 420                         si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
 421                                 #clock-cells = <0>;
 422                                 compatible = "silabs,si570";
 423                                 reg = <0x5d>;
 424                                 temperature-stability = <50>;
 425                                 factory-fout = <300000000>;
 426                                 clock-frequency = <300000000>;
 427                                 clock-output-names = "si570_user_c0";
 428                         };
 429                 };
 430                 i2c_si570_mgt: i2c@3 {
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         reg = <3>;
 434                         si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
 435                                 #clock-cells = <0>;
 436                                 compatible = "silabs,si570";
 437                                 reg = <0x5d>;
 438                                 temperature-stability = <50>;
 439                                 factory-fout = <156250000>;
 440                                 clock-frequency = <148500000>;
 441                                 clock-output-names = "si570_mgt";
 442                         };
 443                 };
 444                 i2c_8a34001: i2c@4 {
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         reg = <4>;
 448                         /* U409B - 8a34001 */
 449                 };
 450                 i2c_clk104: i2c@5 {
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                         reg = <5>;
 454                         /* CLK104_SDA */
 455                 };
 456                 i2c@6 {
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459                         reg = <6>;
 460                         /* RFMCP connector */
 461                 };
 462                 /* 7 NC */
 463         };
 464
 465         i2c-mux@75 {
 466                 compatible = "nxp,pca9548"; /* u22 */
 467                 #address-cells = <1>;
 468                 #size-cells = <0>;
 469                 reg = <0x75>;
 470                 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
 471                 i2c@0 {
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                         reg = <0>;
 475                         /* FMCP_HSPC_IIC */
 476                 };
 477                 i2c_si570_user_c1: i2c@1 {
 478                         #address-cells = <1>;
 479                         #size-cells = <0>;
 480                         reg = <1>;
 481                         si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
 482                                 #clock-cells = <0>;
 483                                 compatible = "silabs,si570";
 484                                 reg = <0x5d>;
 485                                 temperature-stability = <50>;
 486                                 factory-fout = <300000000>;
 487                                 clock-frequency = <300000000>;
 488                                 clock-output-names = "si570_user_c1";
 489                         };
 490                 };
 491                 i2c@2 {
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                         reg = <2>;
 495                         /* SYSMON */
 496                 };
 497                 i2c@3 {
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                         reg = <3>;
 501                         /* DDR4 SODIMM */
 502                 };
 503                 i2c@4 {
 504                         #address-cells = <1>;
 505                         #size-cells = <0>;
 506                         reg = <4>;
 507                         /* SFP3 */
 508                 };
 509                 i2c@5 {
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                         reg = <5>;
 513                         /* SFP2 */
 514                 };
 515                 i2c@6 {
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                         reg = <6>;
 519                         /* SFP1 */
 520                 };
 521                 i2c@7 {
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                         reg = <7>;
 525                         /* SFP0 */
 526                 };
 527         };
 528         /* MSP430 */
 529 };
 530
 531 &qspi {
 532         status = "okay";
 533         is-dual = <1>;
 534         flash@0 {
 535                 compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
 536                 #address-cells = <1>;
 537                 #size-cells = <1>;
 538                 reg = <0x0>;
 539                 spi-tx-bus-width = <1>;
 540                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 541                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 542         };
 543 };
 544
 545 &rtc {
 546         status = "okay";
 547 };
 548
 549 &sata {
 550         status = "okay";
 551         /* SATA OOB timing settings */
 552         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 553         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 554         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 555         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 556         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 557         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 558         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 559         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 560         phy-names = "sata-phy";
 561         phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
 562 };
 563
 564 /* SD1 with level shifter */
 565 &sdhci1 {
 566         status = "okay";
 567         disable-wp;
 568         /*
 569          * This property should be removed for supporting UHS mode
 570          */
 571         no-1-8-v;
 572         xlnx,mio_bank = <1>;
 573 };
 574
 575 &serdes {
 576         status = "okay";
 577 };
 578
 579 &uart0 {
 580         status = "okay";
 581 };
 582
 583 /* ULPI SMSC USB3320 */
 584 &usb0 {
 585         status = "okay";
 586 };
 587
 588 &dwc3_0 {
 589         status = "okay";
 590         dr_mode = "host";
 591         snps,usb3_lpm_capable;
 592         phy-names = "usb3-phy";
 593         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 594 };