arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  *
   5  * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
   6  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   7  * Copyright (C) 2020 Marek Vasut <marex@denx.de>
   8  */
   9
  10 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  11 #include "stm32mp15-u-boot.dtsi"
  12 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
  13 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  14 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  15
  16 / {
  17         u-boot,dm-pre-reloc;
  18         config {
  19                 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
  20                 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
  21         };
  22 };
  23
  24 &gpiof {
  25         snor-nwp {
  26                 gpio-hog;
  27                 gpios = <7 0>;
  28                 output-high;
  29                 line-name = "spi-nor-nwp";
  30         };
  31 };
  32
  33 &i2c4 {
  34         u-boot,dm-pre-reloc;
  35 };
  36
  37 &i2c4_pins_a {
  38         u-boot,dm-pre-reloc;
  39         pins {
  40                 u-boot,dm-pre-reloc;
  41         };
  42 };
  43
  44 &pmic {
  45         u-boot,dm-pre-reloc;
  46 };
  47
  48 &qspi {
  49         u-boot,dm-spl;
  50 };
  51
  52 &rcc {
  53         st,clksrc = <
  54                 CLK_MPU_PLL1P
  55                 CLK_AXI_PLL2P
  56                 CLK_MCU_PLL3P
  57                 CLK_PLL12_HSE
  58                 CLK_PLL3_HSE
  59                 CLK_PLL4_HSE
  60                 CLK_RTC_LSE
  61                 CLK_MCO1_DISABLED
  62                 CLK_MCO2_DISABLED
  63         >;
  64
  65         st,clkdiv = <
  66                 1 /*MPU*/
  67                 0 /*AXI*/
  68                 0 /*MCU*/
  69                 1 /*APB1*/
  70                 1 /*APB2*/
  71                 1 /*APB3*/
  72                 1 /*APB4*/
  73                 2 /*APB5*/
  74                 23 /*RTC*/
  75                 0 /*MCO1*/
  76                 0 /*MCO2*/
  77         >;
  78
  79         st,pkcs = <
  80                 CLK_CKPER_HSE
  81                 CLK_FMC_ACLK
  82                 CLK_QSPI_ACLK
  83                 CLK_ETH_DISABLED
  84                 CLK_SDMMC12_PLL4P
  85                 CLK_DSI_DSIPLL
  86                 CLK_STGEN_HSE
  87                 CLK_USBPHY_HSE
  88                 CLK_SPI2S1_PLL3Q
  89                 CLK_SPI2S23_PLL3Q
  90                 CLK_SPI45_HSI
  91                 CLK_SPI6_HSI
  92                 CLK_I2C46_HSI
  93                 CLK_SDMMC3_PLL4P
  94                 CLK_USBO_USBPHY
  95                 CLK_ADC_CKPER
  96                 CLK_CEC_LSE
  97                 CLK_I2C12_HSI
  98                 CLK_I2C35_HSI
  99                 CLK_UART1_HSI
 100                 CLK_UART24_HSI
 101                 CLK_UART35_HSI
 102                 CLK_UART6_HSI
 103                 CLK_UART78_HSI
 104                 CLK_SPDIF_PLL4P
 105                 CLK_FDCAN_PLL4R
 106                 CLK_SAI1_PLL3Q
 107                 CLK_SAI2_PLL3Q
 108                 CLK_SAI3_PLL3Q
 109                 CLK_SAI4_PLL3Q
 110                 CLK_RNG1_LSI
 111                 CLK_RNG2_LSI
 112                 CLK_LPTIM1_PCLK1
 113                 CLK_LPTIM23_PCLK3
 114                 CLK_LPTIM45_LSE
 115         >;
 116
 117         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 118         pll1: st,pll@0 {
 119                 compatible = "st,stm32mp1-pll";
 120                 reg = <0>;
 121                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 122                 frac = < 0x800 >;
 123                 u-boot,dm-pre-reloc;
 124         };
 125
 126         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 127         pll2: st,pll@1 {
 128                 compatible = "st,stm32mp1-pll";
 129                 reg = <1>;
 130                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 131                 frac = < 0x1400 >;
 132                 u-boot,dm-pre-reloc;
 133         };
 134
 135         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 136         pll3: st,pll@2 {
 137                 compatible = "st,stm32mp1-pll";
 138                 reg = <2>;
 139                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 140                 frac = < 0x1a04 >;
 141                 u-boot,dm-pre-reloc;
 142         };
 143
 144         /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
 145         pll4: st,pll@3 {
 146                 compatible = "st,stm32mp1-pll";
 147                 reg = <3>;
 148                 cfg = < 1 49 5 11 5 PQR(1,1,1) >;
 149                 u-boot,dm-pre-reloc;
 150         };
 151 };