arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019 Marek Vasut <marex@denx.de>
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp15-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
   9 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  10 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  11
  12 / {
  13         aliases {
  14                 i2c1 = &i2c2;
  15                 i2c3 = &i2c4;
  16                 i2c4 = &i2c5;
  17                 mmc0 = &sdmmc1;
  18                 mmc1 = &sdmmc2;
  19                 spi0 = &qspi;
  20                 usb0 = &usbotg_hs;
  21         };
  22
  23         config {
  24                 u-boot,boot-led = "heartbeat";
  25                 u-boot,error-led = "error";
  26                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  27                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  28                 dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
  29                 dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
  30         };
  31
  32         led {
  33                 red {
  34                         label = "error";
  35                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  36                         default-state = "off";
  37                         status = "okay";
  38                 };
  39
  40                 blue {
  41                         default-state = "on";
  42                 };
  43         };
  44
  45         /* This is actually on FMC2, but we do not have bus driver for that */
  46         ksz8851: ks8851mll@64000000 {
  47                 compatible = "micrel,ks8851-mll";
  48                 reg = <0x64000000 0x20000>;
  49         };
  50 };
  51
  52 &gpiof {
  53         snor-nwp {
  54                 gpio-hog;
  55                 gpios = <7 0>;
  56                 output-high;
  57                 line-name = "spi-nor-nwp";
  58         };
  59 };
  60
  61 &i2c4 {
  62         u-boot,dm-pre-reloc;
  63 };
  64
  65 &i2c4_pins_a {
  66         u-boot,dm-pre-reloc;
  67         pins {
  68                 u-boot,dm-pre-reloc;
  69         };
  70 };
  71
  72 &pinctrl {
  73         /* These should bound to FMC2 bus driver, but we do not have one */
  74         pinctrl-0 = <&fmc_pins_b>;
  75         pinctrl-1 = <&fmc_sleep_pins_b>;
  76         pinctrl-names = "default", "sleep";
  77
  78         fmc_pins_b: fmc-0 {
  79                 pins1 {
  80                         pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
  81                                  <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
  82                                  <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
  83                                  <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
  84                                  <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
  85                                  <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
  86                                  <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
  87                                  <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
  88                                  <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
  89                                  <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
  90                                  <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
  91                                  <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
  92                                  <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
  93                                  <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
  94                                  <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
  95                                  <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
  96                                  <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
  97                                  <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
  98                                  <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
  99                                  <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
 100                                  <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
 101                         bias-disable;
 102                         drive-push-pull;
 103                         slew-rate = <3>;
 104                 };
 105         };
 106
 107         fmc_sleep_pins_b: fmc-sleep-0 {
 108                 pins {
 109                         pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
 110                                  <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
 111                                  <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
 112                                  <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
 113                                  <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
 114                                  <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
 115                                  <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
 116                                  <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
 117                                  <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
 118                                  <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
 119                                  <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
 120                                  <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
 121                                  <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
 122                                  <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
 123                                  <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
 124                                  <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
 125                                  <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
 126                                  <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
 127                                  <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
 128                                  <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
 129                                  <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
 130                 };
 131         };
 132 };
 133
 134 &pmic {
 135         u-boot,dm-pre-reloc;
 136 };
 137
 138 &flash0 {
 139         u-boot,dm-spl;
 140 };
 141
 142 &qspi {
 143         u-boot,dm-spl;
 144 };
 145
 146 &qspi_clk_pins_a {
 147         u-boot,dm-spl;
 148         pins {
 149                 u-boot,dm-spl;
 150         };
 151 };
 152
 153 &qspi_bk1_pins_a {
 154         u-boot,dm-spl;
 155         pins1 {
 156                 u-boot,dm-spl;
 157         };
 158         pins2 {
 159                 u-boot,dm-spl;
 160         };
 161 };
 162
 163 &qspi_bk2_pins_a {
 164         u-boot,dm-spl;
 165         pins1 {
 166                 u-boot,dm-spl;
 167         };
 168         pins2 {
 169                 u-boot,dm-spl;
 170         };
 171 };
 172
 173 &rcc {
 174         st,clksrc = <
 175                 CLK_MPU_PLL1P
 176                 CLK_AXI_PLL2P
 177                 CLK_MCU_PLL3P
 178                 CLK_PLL12_HSE
 179                 CLK_PLL3_HSE
 180                 CLK_PLL4_HSE
 181                 CLK_RTC_LSE
 182                 CLK_MCO1_DISABLED
 183                 CLK_MCO2_DISABLED
 184         >;
 185
 186         st,clkdiv = <
 187                 1 /*MPU*/
 188                 0 /*AXI*/
 189                 0 /*MCU*/
 190                 1 /*APB1*/
 191                 1 /*APB2*/
 192                 1 /*APB3*/
 193                 1 /*APB4*/
 194                 2 /*APB5*/
 195                 23 /*RTC*/
 196                 0 /*MCO1*/
 197                 0 /*MCO2*/
 198         >;
 199
 200         st,pkcs = <
 201                 CLK_CKPER_HSE
 202                 CLK_FMC_ACLK
 203                 CLK_QSPI_ACLK
 204                 CLK_ETH_PLL4P
 205                 CLK_SDMMC12_PLL4P
 206                 CLK_DSI_DSIPLL
 207                 CLK_STGEN_HSE
 208                 CLK_USBPHY_HSE
 209                 CLK_SPI2S1_PLL3Q
 210                 CLK_SPI2S23_PLL3Q
 211                 CLK_SPI45_HSI
 212                 CLK_SPI6_HSI
 213                 CLK_I2C46_HSI
 214                 CLK_SDMMC3_PLL4P
 215                 CLK_USBO_USBPHY
 216                 CLK_ADC_CKPER
 217                 CLK_CEC_LSE
 218                 CLK_I2C12_HSI
 219                 CLK_I2C35_HSI
 220                 CLK_UART1_HSI
 221                 CLK_UART24_HSI
 222                 CLK_UART35_HSI
 223                 CLK_UART6_HSI
 224                 CLK_UART78_HSI
 225                 CLK_SPDIF_PLL4P
 226                 CLK_FDCAN_PLL4R
 227                 CLK_SAI1_PLL3Q
 228                 CLK_SAI2_PLL3Q
 229                 CLK_SAI3_PLL3Q
 230                 CLK_SAI4_PLL3Q
 231                 CLK_RNG1_LSI
 232                 CLK_RNG2_LSI
 233                 CLK_LPTIM1_PCLK1
 234                 CLK_LPTIM23_PCLK3
 235                 CLK_LPTIM45_LSE
 236         >;
 237
 238         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 239         pll1: st,pll@0 {
 240                 compatible = "st,stm32mp1-pll";
 241                 reg = <0>;
 242                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 243                 frac = < 0x800 >;
 244                 u-boot,dm-pre-reloc;
 245         };
 246
 247         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 248         pll2: st,pll@1 {
 249                 compatible = "st,stm32mp1-pll";
 250                 reg = <1>;
 251                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 252                 frac = < 0x1400 >;
 253                 u-boot,dm-pre-reloc;
 254         };
 255
 256         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 257         pll3: st,pll@2 {
 258                 compatible = "st,stm32mp1-pll";
 259                 reg = <2>;
 260                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 261                 frac = < 0x1a04 >;
 262                 u-boot,dm-pre-reloc;
 263         };
 264
 265         /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
 266         pll4: st,pll@3 {
 267                 compatible = "st,stm32mp1-pll";
 268                 reg = <3>;
 269                 cfg = < 1 49 11 11 11 PQR(1,1,1) >;
 270                 u-boot,dm-pre-reloc;
 271         };
 272 };
 273
 274 &sdmmc1 {
 275         u-boot,dm-spl;
 276 };
 277
 278 &sdmmc1_b4_pins_a {
 279         u-boot,dm-spl;
 280         pins1 {
 281                 u-boot,dm-spl;
 282         };
 283         pins2 {
 284                 u-boot,dm-spl;
 285         };
 286 };
 287
 288 &sdmmc1_dir_pins_a {
 289         u-boot,dm-spl;
 290         pins1 {
 291                 u-boot,dm-spl;
 292         };
 293         pins2 {
 294                 u-boot,dm-spl;
 295         };
 296 };
 297
 298 &sdmmc2 {
 299         u-boot,dm-spl;
 300 };
 301
 302 &sdmmc2_b4_pins_a {
 303         u-boot,dm-spl;
 304         pins {
 305                 u-boot,dm-spl;
 306         };
 307 };
 308
 309 &sdmmc2_d47_pins_a {
 310         u-boot,dm-spl;
 311         pins {
 312                 u-boot,dm-spl;
 313         };
 314 };
 315
 316 &uart4 {
 317         u-boot,dm-pre-reloc;
 318 };
 319
 320 &uart4_pins_a {
 321         u-boot,dm-pre-reloc;
 322         pins1 {
 323                 u-boot,dm-pre-reloc;
 324         };
 325         pins2 {
 326                 u-boot,dm-pre-reloc;
 327                 /* pull-up on rx to avoid floating level */
 328                 bias-pull-up;
 329         };
 330 };