arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp15-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
   9
  10 / {
  11         aliases {
  12                 i2c3 = &i2c4;
  13                 mmc0 = &sdmmc1;
  14                 mmc1 = &sdmmc2;
  15         };
  16
  17         config {
  18                 u-boot,boot-led = "heartbeat";
  19                 u-boot,error-led = "error";
  20                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  21                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  22         };
  23
  24         led {
  25                 red {
  26                         label = "error";
  27                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  28                         default-state = "off";
  29                         status = "okay";
  30                 };
  31         };
  32 };
  33
  34 &clk_hse {
  35         st,digbypass;
  36 };
  37
  38 &i2c4 {
  39         u-boot,dm-pre-reloc;
  40 };
  41
  42 &i2c4_pins_a {
  43         u-boot,dm-pre-reloc;
  44         pins {
  45                 u-boot,dm-pre-reloc;
  46         };
  47 };
  48
  49 &pmic {
  50         u-boot,dm-pre-reloc;
  51 };
  52
  53 &rcc {
  54         st,clksrc = <
  55                 CLK_MPU_PLL1P
  56                 CLK_AXI_PLL2P
  57                 CLK_MCU_PLL3P
  58                 CLK_PLL12_HSE
  59                 CLK_PLL3_HSE
  60                 CLK_PLL4_HSE
  61                 CLK_RTC_LSE
  62                 CLK_MCO1_DISABLED
  63                 CLK_MCO2_DISABLED
  64         >;
  65
  66         st,clkdiv = <
  67                 1 /*MPU*/
  68                 0 /*AXI*/
  69                 0 /*MCU*/
  70                 1 /*APB1*/
  71                 1 /*APB2*/
  72                 1 /*APB3*/
  73                 1 /*APB4*/
  74                 2 /*APB5*/
  75                 23 /*RTC*/
  76                 0 /*MCO1*/
  77                 0 /*MCO2*/
  78         >;
  79
  80         st,pkcs = <
  81                 CLK_CKPER_HSE
  82                 CLK_FMC_ACLK
  83                 CLK_QSPI_ACLK
  84                 CLK_ETH_DISABLED
  85                 CLK_SDMMC12_PLL4P
  86                 CLK_DSI_DSIPLL
  87                 CLK_STGEN_HSE
  88                 CLK_USBPHY_HSE
  89                 CLK_SPI2S1_PLL3Q
  90                 CLK_SPI2S23_PLL3Q
  91                 CLK_SPI45_HSI
  92                 CLK_SPI6_HSI
  93                 CLK_I2C46_HSI
  94                 CLK_SDMMC3_PLL4P
  95                 CLK_USBO_USBPHY
  96                 CLK_ADC_CKPER
  97                 CLK_CEC_LSE
  98                 CLK_I2C12_HSI
  99                 CLK_I2C35_HSI
 100                 CLK_UART1_HSI
 101                 CLK_UART24_HSI
 102                 CLK_UART35_HSI
 103                 CLK_UART6_HSI
 104                 CLK_UART78_HSI
 105                 CLK_SPDIF_PLL4P
 106                 CLK_FDCAN_PLL4R
 107                 CLK_SAI1_PLL3Q
 108                 CLK_SAI2_PLL3Q
 109                 CLK_SAI3_PLL3Q
 110                 CLK_SAI4_PLL3Q
 111                 CLK_RNG1_LSI
 112                 CLK_RNG2_LSI
 113                 CLK_LPTIM1_PCLK1
 114                 CLK_LPTIM23_PCLK3
 115                 CLK_LPTIM45_LSE
 116         >;
 117
 118         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 119         pll1: st,pll@0 {
 120                 compatible = "st,stm32mp1-pll";
 121                 reg = <0>;
 122                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 123                 frac = < 0x800 >;
 124                 u-boot,dm-pre-reloc;
 125         };
 126
 127         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 128         pll2: st,pll@1 {
 129                 compatible = "st,stm32mp1-pll";
 130                 reg = <1>;
 131                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 132                 frac = < 0x1400 >;
 133                 u-boot,dm-pre-reloc;
 134         };
 135
 136         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 137         pll3: st,pll@2 {
 138                 compatible = "st,stm32mp1-pll";
 139                 reg = <2>;
 140                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 141                 frac = < 0x1a04 >;
 142                 u-boot,dm-pre-reloc;
 143         };
 144
 145         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 146         pll4: st,pll@3 {
 147                 compatible = "st,stm32mp1-pll";
 148                 reg = <3>;
 149                 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 150                 u-boot,dm-pre-reloc;
 151         };
 152 };
 153
 154 &sdmmc1 {
 155         u-boot,dm-spl;
 156 };
 157
 158 &sdmmc1_b4_pins_a {
 159         u-boot,dm-spl;
 160         pins1 {
 161                 u-boot,dm-spl;
 162         };
 163         pins2 {
 164                 u-boot,dm-spl;
 165         };
 166 };
 167
 168 &sdmmc1_dir_pins_a {
 169         u-boot,dm-spl;
 170         pins1 {
 171                 u-boot,dm-spl;
 172         };
 173         pins2 {
 174                 u-boot,dm-spl;
 175         };
 176 };
 177
 178 &sdmmc2 {
 179         u-boot,dm-spl;
 180 };
 181
 182 &sdmmc2_b4_pins_a {
 183         u-boot,dm-spl;
 184         pins1 {
 185                 u-boot,dm-spl;
 186         };
 187         pins2 {
 188                 u-boot,dm-spl;
 189         };
 190 };
 191
 192 &sdmmc2_d47_pins_a {
 193         u-boot,dm-spl;
 194         pins {
 195                 u-boot,dm-spl;
 196         };
 197 };
 198
 199 &uart4 {
 200         u-boot,dm-pre-reloc;
 201 };
 202
 203 &uart4_pins_a {
 204         u-boot,dm-pre-reloc;
 205         pins1 {
 206                 u-boot,dm-pre-reloc;
 207         };
 208         pins2 {
 209                 u-boot,dm-pre-reloc;
 210                 /* pull-up on rx to avoid floating level */
 211                 bias-pull-up;
 212         };
 213 };